How to deal with latch setup & hold time problems?

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heligb

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In my design a latch is needed, but its enable signal is generated from several input signals. and the data signal is generated from several input signals too.
It brings setup & hold time problems.

How to write a synthesis script to deal with it?
 

Hi heligb,

STA tool use timing borrow automaticly handle this.
 

To DFF, I can create a clock, and define the min & max library. The DFF setup & hold time problems can be solved by DC. But it is latch, how to deal with it?
I search it in synopsys sold, but nothing found.
 

I think you need not worry about it
latch is not the same with ff
ff only sample data at the posedge(or negedge) of clock
but for latch, when the data and enable are stable, the data can be latched correcttly
if i am wrong, please correct me, i did not design such circuits
 

No, the latch also have a lauch edge. If a latch's enable signal is high active, the negative edge is the lauch edge.

Setup time: the data must be stable time before the edge
Hold time: the data must be stable time after the edge
 
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    vngo

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at max, we should try to avoid the usage of latches. they leads to more problems in backend stage.

PT can solve this using time borrowing.
 

You need to put you enable signal through the register and you data signal as well
somethin like this

process (clk)
begin
if (clk = '1' and clk'event)
latch_en <= a and b or c;
data_in <= d or e or f;
end if;
end process;

process(clk)
begin
if (clk = '1' and clk'event) then
if latch_en = '1' them
data_out <= data_in;
end if;
end if;
end process;
 

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