joinfaisal
Member level 2
inout ports in VHDL
hello all..
Can any one tell me how to deal with inout port in vhdl.
I have a model like this
if(sel='1' and sel_not='0')then
Y <= X
else
Y <= '0';
now I want to do this bidirectionaly ie on same sel and sel_not signals...if we have input from Y then it should go to X.I declared X and Y inout and used another process like this
if(sel='1' and sel_not='0') then
X <= Y
else
X <='0';
now problem is this gives 'X' when simulating.I know the reason of this problem but I dont know proper way to do it.Can any one help...thnxxx in advance.
hello all..
Can any one tell me how to deal with inout port in vhdl.
I have a model like this
if(sel='1' and sel_not='0')then
Y <= X
else
Y <= '0';
now I want to do this bidirectionaly ie on same sel and sel_not signals...if we have input from Y then it should go to X.I declared X and Y inout and used another process like this
if(sel='1' and sel_not='0') then
X <= Y
else
X <='0';
now problem is this gives 'X' when simulating.I know the reason of this problem but I dont know proper way to do it.Can any one help...thnxxx in advance.