How to create the SDF & VHDL netlist for ModelSim SE 5.7

[GoodMan]

ise sdf

How to create the SDF & VHDL netlist for ModelSim SE 5.7X in Xilinx ISE5.1i ?
Who can teach me ?
If you have some info doc,please tell me!

have a nice day!

 

[Ohh]

how to create netlist for vhdl

After you have performed the place and route step in the Xilinx ISE, you can generate a netlist and SDF file for timing simulation with ModelSim XE. This can be easily done by double-clicking on the corresponding menu on the left-hand side. The manual provided by Xilinx also describes how to do this.

 

[simon2kk]

sdf modelsim

In Xilinx ISE 5.1i, double-click on "Generate Post-place & route simulation model". This will generate the sdf and vhdl for Modelsim.

simon2kk

 

[GoodMan]

xilinx ise sdf

I have a new problem.when I created SDF and netlist,but how to create
library of SpartanII FPGA for Modelsim SE. :lol:
I can create a library of Altera FPGA,but I don't know the flow of Xilinx FPGA library for ModelSim SE.
If anyone have a easy method to create SpartanII library,Plz help me :!:

thx! :wink:

 

[Ohh]

modelsim + procedure

If you don't use ModelSim Xilinx Edition, you must have a library called simprim which is required to perform the post-P&R timing simulation.

 

[arena_yang]

sdf edf vhdl

Typically, all the FPGA vendors' integrated development enviorement will all automatically generate a *.sdf file and a new *.vhd file which includes the specific FPGA device info and the time delay info etc.
In ISE5.1/2i, it will generate a file like mydesign_timesim.vhd

So if we want to post-simulate a design, we should only need to add the *timesim.vhd and the testbench files in the Modelsim.

And Of course, we should add the device library info into the Modelsim, In ISE5.1i/2i, go to the directory \bin\nt, run "compxlib -help", you will find how to compile the device lib into Modelsim.

BTWoes anybody know how to compile Altera device lib into Modelsim?

 

[kil]

ise timing sdf

hi all,

after generating the post place and route timingfiles (*.sdf and *.vho) then what are the steps for simulating for timing using the testbench. do i need to change any modifications in the testbench for post p&r timing simulation to the testbench which i have written for simulation purpsoe.


regards
kil

 

[deepakagarwal]

too many port connections. modelsim

no you dont have to modify your test bench for post par.....just call .sdf file in model sim....procedure you can find in Help menu ... coz this depends on your version....let me know if you r facing any problem after doing this ....

 

[FLEXcertifydll]

ise sdf vhdl

U can generate the SDF and netlist file thro "Generate Post-place & route simulation model".
And U can find the post-simulation library in ISE install directory.

 

[radon]

creat netlist with modelsim

I am a facing a rather strange problem.
I want to do post place and route simulation for my design targetted for xilinx virtex 4.
I am using ISE 10.1, I have generated the post place and route model (_timesim.v) and sdf.
I have also generated simprim library using ISE for modelsim 6.1d.
While compiling, the modules ( testbench, uut and glbl) are compiled without any errors. Also, the modules defined in the library file 'simprims_ver_source.v' are also compiled successfully.
But when I try to load my top module, then I get a really strange error:
** Fatal: (vsim-3365) C:/Modeltech_6.1d/examples/gentest_timesim.v(27344): Too many port connections. Expected 5, found 14.
I have seen the line number 27344, it is like:
X_LUT4 #(
.INIT ( 16'h32C8 ),
.LOC ( "SLICE_X36Y141" ))
\r1/module_ktorpvc/lula/m2/eindxdash<2>6811 (
.ADR0(\r1/module_ktorpvc/lula/m1/c4 [13]),
.ADR1(\r1/module_ktorpvc/la/rr1/endm_7673 ),
.ADR2(\r1/module_ktorpvc/c ),
.ADR3(\r1/module_ktorpvc/two_7672 ),
.O(\r1/module_ktorpvc/lula/m2/eindxdash<2>681 )
);
As it is evident, the above instantiation has asked for only 5 ports, also the X_LUT4 definition has 5 ports. I am not able to understand why I am getting the error "Too many port connections. Expected 5, found 14."
I am not able to proceed because of this.
Please help