I advise two methods, hope helpful for you.
(1) If you need accurate result, then you need to use the GDS to do the RC extraction, then use the
generated RC Hspice netlist to do the transistor level simulation.
(2) If you just need run a Hspice simulation, without high requirement on the accuracy. Then you can use "nettran" (in Heculus) or "v2lvs" (in Calibre) to transform the verilog netlist into the Hspice netlist. To keep the accuracy, some CShunt may be added according to the technology library used.
Good luck...