How to create a VHDL library and use it.

[anonymous.]

There are lots of components that are really much used in designs (Muxes,Buffers, etc). rewriting them each time or copying files from project to project is nonsense.
I want to create a VHDL library and save these components in it. I've searched about this and I can't find a good reference on this. can any body help me on creaing a library, adding files or components and using them?

 

[rajavel.rv]

VHDL not support for creating a component inside of PACKAGE DECLARATION AND PACKAGE BODY. U can use as a function declaration and function calling its help full for u.

 

[sherif123]

No, I think you can write the component declaration inside the package declaration (not the package body).

example

package mypack is

component comp is
port(
.................
);
end component;

end;

package body mypack is

end package body;

and then you can instantiate the component in the top module but first write
use work.mypack.all;
in the top file where u want to instantiate the component.

 

[rajavel.rv]

k nice, its successfully compiling. But wherever we can use this component calling and how can it was instantiated. and what is the syntax for that (i.e) port map..

 

[sherif123]

Sorry I could not understand your reply, rajavel.rv . But I think you ask about how to instantiate a component in another file
You instantiate it like any other component whether the component in defined in a package or in the file itself
Anyway, you do instantiation like this

block_obj: module
port map (
...........
);