I am a beginner in VHDL coding.I created a program with lot of portmapping. The program contains 28 components.the last program (top one) is called TOP entity.Now i want to use this TOP entity as a function??how can i do it ??can i use entity inside function declaration??
Oh you want to use your top module as a function & use it in some other file.Maybe you want to do it the way they do it with library files.
you can create a new file & in that new file you declare the function & type in the body as you would normally do in a function declaration,
Oh you want to use your top module as a function & use it in some other file.Maybe you want to do it the way they do it with library files.
you can create a new file & in that new file you declare the function & type in the body as you would normally do in a function declaration,
can I use portmapping inside the function body??my program is a reconfigurable multiplier.it is having atleast 12 levels.how can i convert this big program into a function.that is my question.
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Syedshan
i have a program which is having many levels.12 levels.now i want to use the program as a function.now how can i convert a normal program to a function.my program contains lot of portmapping.so how can i realise the function??.i searched for the examples in net.but nothing is there
i have a program which is having many levels.12 levels.now i want to use the program as a function.now how can i convert a normal program to a function.my program contains lot of portmapping.so how can i realise the function??.i searched for the examples in net.but nothing is there
I guess by levels he mean, pipeline stages, am I right TrickyDicky?
As far as I have understood your problem, it is that you have already made a program (module) and now you want to invoke it into you code at after some incident. Hence, like we used to do in c, i.e. we call function you want to have this same scenario. Unfortunately it is not possible in HDLs, hence what you can do is you should put enable signals in your module (which you want as a function) and then control the data-flow INTO the module using this enable pin. After some event, enable pin gets activated for required time-cycles and hence data is captured by your instantiated entity and hence you have your desired operation performed.
can you also post your code here. Both top-level and inner entities.
The VHDL way of inserting the present design in an embedding hierarchy is to instantiate the top entity as a component, as already mentioned.
The most important restriction of VHDL subprograms (functions, procedures) related to your question is that they only implement pure combinational logic, no registers and hence can't use a clock. So if your design is purely combinational and memoryless, it can be converted into a subprogram, otherwise it can't.
I remember one of my design having more than 25 instances under Top level module. Never mind about these functions\procedures in this context. You can safely forget that
View attachment Vedic Multiplier.doc
this is my program.it is a vedic multiplier which is purely combinational. now i want to create a RSA encryptor.
so i need a number of multipliers for encryption.I am using a for loop inside which i need to have many vedic multipliers.now how can i use this vedic multiplier inside a for loop??can i convert it to a function??.I have included the code
you cannot use entities inside a for loop. You could instantiate them inside a for generate loop though, as you're just instantiating them all in parrallel.
You do seem to be making your life difficult though. Why are you making every basic thing (like an XOR) a separate entity. why not just do