Re: verilog to schematic
Hello,
you are referring to Quartus RTL viewer. But it's view hasn't a touch of HDL to my opinion. Of course you could produce *.bdf graphics, that look as confuse as RTL viewer output (or should say, you are hopefully not able to), but I believe, that's not what mhamed is looking for.
If you have the design in mind and want to check a detail of implementation, then RTL viewer could be helpful and you are able to navigate. The good thing with RTL viewer is, that it preserves hierarchies.
Thus I think, for the project there is no way but learning to read the Verilog code. If it's not in an appropriate readable form, then to extract the basic structure and algoritms on your own.
Regards,
Frank