How to convert this vhdl code to verilog ?

[allanjose7890]

This is an array of 1024 bytes which is of11bits

---

Code VHDL - [expand]
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architecture RTL of ENC8B10B is
 
type TYPE_ENC8b10b is array (0 to 1023) of std_logic_vector (10 downto 0); -- RD & Dx.y
signal TBL_ENC8b10b : TYPE_ENC8b10b:=
  (
  --    "Rjhgfiedcba"   -- RD(Pre) + Dx.y => RD(Post)
    "00010111001",  -- "00000000" -D00.0- [0]
    "00010101110",  -- "00000001" -D01.0- [1]
    "00010101101",  -- "00000010" -D02.0- [2]
    "11101100011",  -- "00000011" -D03.0+ [3]
    "00010101011",  -- "00000100" -D04.0- [4]
    "11101100101",  -- "00000101" -D05.0+ [5]
    "11101100110",  -- "00000110" -D06.0+ [6]
    "11101000111",  -- "00000111" -D07.0+ [7]
    "00010100111",  -- "00001000" -D08.0- [8]
    "11101101001",  -- "00001001" -D09.0+ [9]

---

 

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If your tool chains can support SV then...
http://stackoverflow.com/questions/23163042/when-to-use-the-tick-for-verilog-array-initialization

If you have to use Verilog only then see the the 3rd post (and yes I know this is for Xilinx, but Xilinx is notorious for not supporting new language features)...
http://forums.xilinx.com/t5/General-Technical-Discussion/Initializing-a-two-dimentional-array-in-verilog/td-p/175884