Refer to cadence tutorial. You can get the netlist file of your layout only if there is a schematic corresponding to your layout. Check with some import option in menu.
Also Xilinx ISE simulator is the best for doing timing analysis either by VHDL or Verilog code.
That's not quite correct, I think: The extraction tool (diva, assura, calibre) can extract a netlist from a layout -- it doesn't need a corresponding schematic for this. Only the LVS tool needs it.
If the layout has correctly labeled node and pin names, the extracted netlist will contain these.