Hello Friends!
Sorry my connection from server was down for a day. ok I'm doing a project on SDR. The idea about developing is all by mine(it's just a prototype).I have the following peripherals in my Mainboard.
1) Xilinx Virtex 4 FPGA
2) Adjustable master clock from 1 MHZ to 100MHz.
3) 40MHz ADC/125MHz Dac*
4) Codec(2 ch)**
5) XILINX ISE 8.2i, Modelsim6
* ADC\DAC has it's own filter circuits. It's bipolar device,have range 2Vpp
**Codec again has filter circuits built around it. So codec offset error can be rejected
In my project(On FPGA only) there are different layers of operations inside FPGA
Layer 1 :- DATA from Codec @ 2MHz bit rate contains 16 Lch + 16 Rch(32bits)
Layer 2 :- Adding header,marker,checksum(CRC)
Layer 3 :- CODING (Manchester,NRZ,8b\10b,etc if any)
Layer 4 :- MODULATION & DEMODULATION
TRANSMISSION : LAYER1 ---> LAYER2 ---> LAYER3 ---> LAYER 4 ---> RF
RECEPTION : LAYER1 <--- LAYER2 <--- LAYER3 <--- LAYER 4 <--- RF
Layer 1:-
In this part I have completed all IN\OUT of a standard Voice codec using AD73322. I sample the data at 16KHz and use 2MHz bit clock with 8us time between sync1 and sync2. But the total time is 64us. The codec sends data at the rate of 2MHz.It continuously sends the ch1(16 bits) at 8us and ch2(16bits) at 8us. Total sampling time is 64us. Out of this,there are remaining 48us. IN this time i add marker and other overheads in steps.My target time is to achieve all this work done including modulation within that time. Orelse I will get data shift or missing at the receiver.This is one reason why I chose 2MHz as the bit clock speed for codec
Layer 2:- STILL TO BE IMPLEMENTED
Layer 3:- STILL TO BE IMPLEMENTED
Layer 4:-
Types of modulation techniqes to be implemented using FPGA on VIRTEX 4
1) ASK(ook type)
2) FSK
3) PSK
4) QPSK
This is the part at which I currently stuck up with.
I have completed ASK modulation easily by using schmitt trigger concept. So demodulation wasn't an issue even at higher freqs like 2 or 4MHz. While I was trying to prove fsk at lower freq around 20KHz/40KHz carrier, I never felt any problem in recovering data from the sine wave at the receiver. When I used 2MHz and 4MHz as my fsk carrier for a data rate of 2MHz, problem shouted a lot more. I send 20 samples at 40MHz to get 2MHz from dac for "1"s and I send 10 samples at 40MHz to get 4MHz from dac for '0's. I keep switching this sine freqs depending on data using CASE statement. so my
data rate = 2MHz
F1 = 2MHz
F2 = 4MHz
Sample execution clock = 40MHz.
so for sending 20 samples,I get 2Mhz and 4MHz for 10 samples
I didn't opt any RF medium til now. All I first need to prove is the modulation technique. So I directly feed this fsk from Tx into the Rx's ADC.So noise based addition is not possible. Here is the problem.Like I said, I thought of converting the fsk stream into sqr wave so that I can lock those two oscillating frequencies very easily. But now I cannot trace the sqr wave of the fsk signal with 50% duty cycle.As a result, I get 1 SQR wave for 1(2MHz) sine with 70% duty cylce and two Sqr waves for 2(4MHz) sine with 70%duty cycle at constant speed. Now if I use counting of ON\Off time technique for recovering 1s and 0s,then the values don't stay constant. As a result the recoverd data has ON time somewhat higher period say 300ns than OFF time say 200ns.So now my data 1s and 0s are not at constant timeperiod.Data '1' But the wonder is that if I feed this output into the other layers,I was able to get the audio back.Why?....This is becasue the codec samples at 2MHz bit clock. My data 1's and 0's are samples at their levels(falling edge of 2MHz clk).So a slight longer ON time doesn't affect the case. But I feel this is not a proper way. I hope you have got about my progress. If you have any doubt in this,plz ask me.I will try to provide more information.I don't know how to post pictures. Or else I could've shown you things with details. Thanks for your time friends..Expecting some better solution....