how to convert integer to bit_vector?

[20vt]

I did a program that counts the ones on a number(6 length) like 011100 the out is 3
but I want the outpot to be in bit_victor (2 down to 0) and not integer
if I input this num 011100 the output should be '011' and not 3

 

[bking]

https://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf

See page 8 of the PDF (or P15 & P16 as the half pages were originally numbered)

 

[std_match]

Take a look at the attached help document about numeric_std.

As you can see, one conversion and one cast are necessary to go from integer to std_logic_vector:

std_logic_vector_signal <= std_logic_vector(to_unsigned(integer_result, std_logic_vector_signal'length));

However, if you don't want the result as integer, I recommend you to use type "unsigned". It is intended to represent a number, but you can do the same bit-manipulation as with std_logic_vector.
Then you only need the "to_unsigned" conversion.

 

[20vt]

LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use IEEE.numeric_std.all;

entity conterone is
port(d:in bit_vector(6 downto 0);
countut integer

) ;
end conterone;

architecture arc_conterone of conterone is
signal x : unsigned (2 downto 0) ;


begin
process(d)
variable c:integer;
begin
c:=0;
for i in 0 to 6 loop
if(d(i)='1')then
c:=c+1;
end if;
end loop;
count <= c ;
x <= to_UNSIGNED (count,3);


end process;
end arc_conterone;

how to convert correctly ?

 

[TrickyDicky]

how to convert correctly ?

First of all, you cannot assign X from the output "count"

But also you need to delete this line:
USE ieee.std_logic_arith.all;

 

[20vt]

so how I do it?
if I remove this library it wont count

 

[20vt]

Its work thanx