Non AMP

how to convert cadance pspice to cadance verlog file ??

Thread starter kabaleevisu
Start date Mar 28, 2011

Status: Not open for further replies.

Mar 28, 2011

#1

K

kabaleevisu

Advanced Member level 2

hI
I AM USING cadance allegro 16.2

i am designing vlsi adders now .how to convert cadance p spice to verilog file

Status: Not open for further replies.

Similar threads

M
How to instantiate another vhd file inside testbench, where the testbench is used for opening files
- Started by metamisers
- Jan 6, 2024
- Replies: 6
PLD, SPLD, GAL, CPLD, FPGA Design
S
Image fusion how to implementing on FPGA
- Started by Sanila P
- May 14, 2024
- Replies: 1
PLD, SPLD, GAL, CPLD, FPGA Design
H
How to store Coco training data set in Pynqz2 board
- Started by hudda
- Yesterday at 12:10 PM
- Replies: 0
PLD, SPLD, GAL, CPLD, FPGA Design
Z
Converting XC7300 .PLD file to .HEX
- Started by Zag4cpld
- Jun 4, 2023
- Replies: 0
PLD, SPLD, GAL, CPLD, FPGA Design
K
explanation of how to translate C code into verilog
- Started by keikaku
- Mar 5, 2024
- Replies: 10
PLD, SPLD, GAL, CPLD, FPGA Design