how to convert 32bit vector to a number

[DNA2683]

how to convert 32bit vector to a real

hi
im new in the VHDL world...

i have a 32bit vector (16bit for integer and 16bit for fraction), the real number that the vector represents(fixed point) can be positive or negative

how can i convert the vector back to a real number?

 

[TrickyDicky]

if you mean real type, you can use the built in functions of the new fixed_point packages:

signal a : sfixed(15 downto -16);
signal b : real;

b <= to_real(a);

 

[DNA2683]

if you mean real type, you can use the built in functions of the new fixed_point packages:

signal a : sfixed(15 downto -16);
signal b : real;

b <= to_real(a);

I have a signal as std_logic_vector 32bit the binary data in the vector represent a real number (like 266.3256 or -751.2354 positive ot negative)...when im running a simulation its hard for my to follow the numbers as present as 32bit vector...

so what i want to do is converting the 32bit vector to a real number( like 266.3256 or -751.2354 positive ot negative) and write it eo a file so i can track the numbers..

thanks

 

[TrickyDicky]

If you give the fixed_point packages a go, you'll make your life a lot easier.
Otherwise you have to write a custom conversion function. There is no standard way to do it, as a std_logic_vector is not meant to be used to represent numbers.

 

[DNA2683]

If you give the fixed_point packages a go, you'll make your life a lot easier.
Otherwise you have to write a custom conversion function. There is no standard way to do it, as a std_logic_vector is not meant to be used to represent numbers.

ok ill try to change the code to Sfixed types but i have a few questions:
1.if i want to represent negative or positive numbers (16 bit integer 16 bit fraction) i need an extra bit for sign bit?( sfixed(16 dwonto -15)?)
2.can i write a sfxied type to FIFO?

 

[TrickyDicky]

1. sfixed is signed fixed, so already contains the sign bit. If your origional number was signed, you only need 15 downto -15. If it was origionally unsigned, use the ufixed (unsigned fixed) type.
2. Yes. If it is an IP core you may need to cast back to std_logic_vector first (there is a to_slv function for that). sfixed/ufixed and std_logic_vector are similar types as they are all arrays of std_logic (as are signed and unsigned).

 

[DNA2683]

1. sfixed is signed fixed, so already contains the sign bit. If your origional number was signed, you only need 15 downto -15. If it was origionally unsigned, use the ufixed (unsigned fixed) type.
2. Yes. If it is an IP core you may need to cast back to std_logic_vector first (there is a to_slv function for that). sfixed/ufixed and std_logic_vector are similar types as they are all arrays of std_logic (as are signed and unsigned).

1.my input in a signed (because I know that the input number is positive or negative )
2.can I use the "&" operator to sfixed type ,I need to do something like this :

a,b,c,d :sfixed (15 downto -16);
.
.
.

Output<= a&b&c&d;

I want to marge it in the output to transfer it to a different model ..

3. Can I multiply 2 sfixed types signals ?

Thanks

 

[TrickyDicky]

1. The signed type is fine, you can convert it to sfixed using the function to_sfixed(X, nhigh, nlow), where nhigh is the MSB index, and nlow is LSB index (so would be 15 and -16 in your case, assuming a 32 bit number with 16 bit integer and 16 fraction.

2. yes you can, but the output must be 128 bits wide. You probably dont want output to be an sfixed type, because its now 4 numbers concatenated. A std_logic_vector would be more appropriate:

output <= to_slv(a&b&c&d);

3. Yes:

a <= b *c;

just make sure the bit sizings are correct:

signal a : sfixed(31 downto -32);
signal b,c : sfixed(15 downto -16);

or use the resize function.

 

[DNA2683]

1. The signed type is fine, you can convert it to sfixed using the function to_sfixed(X, nhigh, nlow), where nhigh is the MSB index, and nlow is LSB index (so would be 15 and -16 in your case, assuming a 32 bit number with 16 bit integer and 16 fraction.

2. yes you can, but the output must be 128 bits wide. You probably dont want output to be an sfixed type, because its now 4 numbers concatenated. A std_logic_vector would be more appropriate:

output <= to_slv(a&b&c&d);

3. Yes:

a <= b *c;

just make sure the bit sizings are correct:

signal a : sfixed(31 downto -32);
signal b,c : sfixed(15 downto -16);

or use the resize function.

First of all thanks for the help..

Ok I'll write the output as a vector..this output is goins to a input(in a different entity)
So the input of this entity also will be a vector..in the second entity I still need to work with the 4 parameters (a b c d as sfixed) so how I separate it for the input and convert it back to sfixed?

Thanks

 

[TrickyDicky]

why not just output the 4 values as sfixed? you can use sfixed on the ports (you can use any types you want).

 

[DNA2683]

why not just output the 4 values as sfixed? you can use sfixed on the ports (you can use any types you want).

Ok I'll try it..I have 1 port 4 output it's now a vector (because some one else wrote it )..

Another question :

I have a (x,y) coordinate that I'm getting in my input(the values of x,y can be negative or positive between -640 to 640)..and I multiply x,y in a input parameter also can be positive or negative between - 3 to 3.

X :in sfixed (15 downto -16);
Y:in sfixed (15 downto -16);
Mult1:in sfixed(1 downto -16);
Mult2:in sfixed(1 downto -16);



Out<= (X*mult1)+(Y*mult2);

How can I define the size of the output?

Because each time I get a different size of the integer part ..and when I tried to define the output as an maximum size(of the integer part-32bit*32bit=64bit) of multiplication the modelsim give me a size error...it's seemed that I need to know the multiplication bit size before I know the inputs

 

[TrickyDicky]

Because your input widths are fixed, you can fix the output too (according to your specification).

according to your specs, output should be:

signal output : sfixed(19 downto -32);

PS. If the multiplier is between -3 to +3, you have the wrong size for you Mult1 and Mult 2. Currently they have a range -2 to 2-2^-16

 

[DNA2683]

Because your input widths are fixed, you can fix the output too (according to your specification).

according to your specs, output should be:

signal output : sfixed(19 downto -32);

PS. If the multiplier is between -3 to +3, you have the wrong size for you Mult1 and Mult 2. Currently they have a range -2 to 2-2^-16

thanks for the help


ill try to explain what my code need to do
i have a picture grid(coordinates (x,y)- 640*480) that im geting as an input x&y ,also im getting a matrix size 3*3 the matrix element im getting for 6 inputs(dudx ,dvdx, u0 ,dudy, dvdy ,u0):

matrix:

dudx dvdx u0
dudy dvdy v0
0 0 1

so in each clock i multeply the matrix in a coordinates :

out _x<= dudx*x+dvdx*y+u0;
out_y<= dudy*x+dvdy*y+u0;


dudx,dvdx,dudy,dvdy are fixed numbers between -3 to 3 (for example 2.9311 or -1.5324)
u0,v0 are fixed numbers between -640 to 640 (for example 533.9311 or -10.5324)
x,y are integer : x range (0-480) y range (0-640)

each time im getting a diffrent coordinates in the x,y inputs and i need to multeply them in the matrix (as above)
and the result i need to send to an output as

main_output<=out _x&out _y;

my problam that i dont understend how to diffene the inputs and output sizes,can you tell me please how to write it?

thanks

 

[TrickyDicky]

I dont really understand the question. Have a go, and post some code, and I can fix the errors. You can pretty much write your equation in VHDL as it is, if you get the types right.

 

[DNA2683]

I dont really understand the question. Have a go, and post some code, and I can fix the errors. You can pretty much write your equation in VHDL as it is, if you get the types right.

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Code VHDL - [expand]
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entity  test is
port(
dudx   : in sfixed(1 downto -16);--fixed numbers between -3 to 3 (for example 2.9311 or -1.5324)
dvdx   : in sfixed(1 downto -16);--fixed numbers between -3 to 3 (for example 2.9311 or -1.5324)
u0     : in sfixed(10 downto -16);--fixed numbers between -640 to 640 (for example 533.9311 or -10.5324)
dudy   : in sfixed(1 downto -16);--fixed numbers between -3 to 3 (for example 2.9311 or -1.5324)
dvdy   : in sfixed(1 downto -16);--fixed numbers between -3 to 3 (for example 2.9311 or -1.5324)
v0     : in sfixed(10 downto -16);--fixed numbers between -640 to 640 (for example 533.9311 or -10.5324)
data_in : in std_logic_vector (19 downto 0); --input data a x&y coordinate(integers that are in 10 bit representation) values of x,y can be                                  --negative or positive between -640 to 640  (10bit for x and 10 bit for y)
 
data_out : out  std_logic_vector (19 downto 0);--???? i d'ont know how to chose the size of the output???
clk   : in std_logic;
);
 
 
 
architecture behave of test is
signal out _x     : sfixed(10 downto -16);???? i d'ont know how to chose the size of this signal???
signal out_y     : sfixed(10 downto -16); ???? i d'ont know how to chose the size of this signal???
signal in_x     : integer range (640 to 0);
signal in_y     :  integer range (640 to 0);
 
 
begin
 
in_x    <= to_integer (data_in (9 downto 0));
in_y    <= to_integer (data_in (19 downto 10));
 
 
 
process (clk)
 
begin
out _x<= dudx*x+dvdx*y+u0;
out_y<= dudy*x+dvdy*y+u0;
 
end process
 
data_out <= to_slv(out _x) & to_slv(out _y);
 
end behave;

---

i have a problem to determine the size of the output,out_x,out_y because i dont know the size of the calculation result and because of that im getting an errors about sizes a stuff

this code is not working I wrote it to explain a little better what I need to perform..

thanks for the help

 

[FvM]

One gets a rough idea what you want to achieve, but many unclear details.

- a lot of input data formats don't match the intended data size. E.g. data_in needs 2*11 instead of 2*10 bits to represent +/- 640, also the du and dv factors need three integer bits for +/- 3 range.
- your asking about necessary output size. It depends on the expected input data range and which resolution you want to keep. E.g. +/-3 * +/- 640 needs 12 integer bits for the possible data range, or apply saturation or scale the result down. You apparently want to discard all fractional result bits.

 

[TrickyDicky]

ok. Lets start with

1. All the dud inputs are the wrong size. They currently only cover -2 to +2. You need (2 downto -16) to cover -4 to +
2. if all the other inputs are sfixed, why are data_in and data_out std_logic_vector?
3. Your process is not a clocked process.
4. To size the vectors, you need to follow these sizing rules:

signal X : sfixed(a downto b)
signal Y : sfixed(c downto d)

For addition, subtraction, op needs to be:
signal OP : sfixed( (larger of a or c) + 1 downto (smaller of b or d) );

for multiplication:
signal OP : sfixed( a + c + 1 downto b + d)

You always know the size of the calculation result as you know the size of the other vectcors. It doesnt matter what the current value is, it just matters what the max/min values are.

 

[DNA2683]

ok. Lets start with

1. All the dud inputs are the wrong size. They currently only cover -2 to +2. You need (2 downto -16) to cover -4 to +
2. if all the other inputs are sfixed, why are data_in and data_out std_logic_vector?
3. Your process is not a clocked process.
4. To size the vectors, you need to follow these sizing rules:

signal X : sfixed(a downto b)
signal Y : sfixed(c downto d)

For addition, subtraction, op needs to be:
signal OP : sfixed( (larger of a or c) + 1 downto (smaller of b or d) );

for multiplication:
signal OP : sfixed( a + c + 1 downto b + d)

You always know the size of the calculation result as you know the size of the other vectcors. It doesnt matter what the current value is, it just matters what the max/min values are.

ok.

1. i understand that i need 2bit for represent the max number 3 and one more bit for sigh total =3bit ..so thats ok ill fix it.

2.im getting te data from a model that I did not write..alll i know that in each clock im gitting a diffrent input the data format is x&y (x11bit y11bit = 22bit input)- the 11 bit represent a integer number (-/+640) Accidentally wrote down 10bit.what i need to do is to take the x and y and multeply them in the other inputs.

3.I know the structure of the writing is not good .but Ill know how to fix it later because my problem is figuring out how I deal with calculations.

4.first of all this is what i need to preform (i made a mistake on the code)

out _x<= dudx*in_x+dvdx*in_y+u0;
out_y<= dudy*in_x+dvdy*in_y+v0;

data_out <= to_slv(out _x) & to_slv(out _y);


4.1 can i do this?to multiply a sfixed with integer?

4.2 i didn't understand how to define the out_x,out_y,data_out sizes can you tell me the code for it? base on my input(in_x,in_y can be
+/- 640 integer all du.. dv.. can be -/+ 3 sfixed


Thanks for the help friends, I appreciate it very much

 

[FvM]

4.1 can i do this?to multiply a sfixed with integer?

It's managed by fixed_pkg overload rules. The integer is automatically converted to a sfixed quantity of required size.

4.2 i didn't understand how to define the out_x,out_y,data_out sizes can you tell me the code for it? base on my input(in_x,in_y can be
+/- 640 integer all du.. dv.. can be -/+ 3 sfixed

It's your job to define the maximum output number range and set the format respectively. Then perform a resize operation with overflow_style = fixed_saturate.

Everything explained in the "Fixed point package user’s guide".

 

[DNA2683]

ok. Lets start with

1. All the dud inputs are the wrong size. They currently only cover -2 to +2. You need (2 downto -16) to cover -4 to +
2. if all the other inputs are sfixed, why are data_in and data_out std_logic_vector?
3. Your process is not a clocked process.
4. To size the vectors, you need to follow these sizing rules:

signal X : sfixed(a downto b)
signal Y : sfixed(c downto d)

For addition, subtraction, op needs to be:
signal OP : sfixed( (larger of a or c) + 1 downto (smaller of b or d) );

for multiplication:
signal OP : sfixed( a + c + 1 downto b + d)

You always know the size of the calculation result as you know the size of the other vectcors. It doesnt matter what the current value is, it just matters what the max/min values are.

i tried your suggestion and its work thanksss

i work with the fixed point pkg and i have 2 more questions:

1.when i simulate my code(with modelsim) i work with the WAVE window,in the resulte signal(sfixed) some times i get a positive number and some time negative so each time in need to change the radix from 16fixed to sign16fixed to see the results correctly (depending on the result I should get),can i do something to make the modelsim do it automaticly (when i'm getting a negative number modelsim will understand it automatically and add the minus sign-and when the number is positive it will show the result without of minus sign)?

2.i want to save the results to a text file.how can i write the result(that is a sfixed signal) to a file as a real number(for example :-352.5482 or 542.2154)?how can i convert it to a real number with sigh as the example?


again thank you very much for the help