How to control testbench using TCL

[vcnvcc]

Hello Friends

I want to know how to control different testbeches using TCL..

for example
say I have counter design and to test that Im writing reset test case, clock generation test case, and so many test cases depends on design..... and i have monitor/ checker as well.

Now how to write a file in TCL which controls my test cases in test bench....what this environment called?

If you can tell me bit more about this with example......
(Already searched on internet but not found)....

thanks....

 

[sarath51]

Hope this link will answer part of u'r question

http://www.altera.com/support/examples/tcl/tcl-modelsim.htm

 

[vcnvcc]

Thanks sarath
I have this documets...but what im looking for is something else...

I want a kind of example, with testbench covering different test cases(vhdl if possible) ...and final TCL script which controls this test bench...if u have any material, any link please upload.


Thanks..

Kind of example------------------from asicworld.com

module counter_tb; // say counter design we have n this is its testbench
reg clk, reset, enable;
wire [3:0] count;

counter U0 (
.clk (clk),
.reset (reset),
.enable (enable),
.count (count)
);

initial
begin
clk = 0;
reset = 0;
enable = 0;
end

always
#5 clk = !clk;

endmodule


///say i have reset n clock test case....

event reset_trigger; // now whts this "event"....in VHDL wht to use
event reset_done_trigger;

initial begin
forever begin
@ (reset_trigger);
@ (negedge clk);
reset = 1;
@ (negedge clk);
reset = 0;
-> reset_done_trigger;
end
end


initial
begin: TEST_CASE
#10 -> reset_trigger;
end

initial
begin: TEST_CASE
#10 -> reset_trigger;
@ (reset_done_trigger);
@ (negedge clk);
enable = 1;
repeat (10) begin
@ (negedge clk);
end
enable = 0;
end

 

[aji_vlsi]

Thanks sarath
I have this documets...but what im looking for is something else...

I want a kind of example, with testbench covering different test cases(vhdl if possible) ...and final TCL script which controls this test bench...if u have any material, any link please upload.

;
end

If you already have the testbench why do you need a TCL testcase/bench? I'm sorry I don't understand the requirement well. TCL can be used as testbench/testcase and we cover this in detail along with lab example(s) in our 1-day course on testbench/verification (see www.noveldv.com). We also go about discussing what are other types of testbenches when to use which type, their relative merits and demerits. If you are interested, drop me an email at cvc.training @gmail.com. We are likely to have a public course this week or early next week in Bangalore.

Ajeetha, CVC
www.noveldv.com

 

[vcnvcc]

aji_vlsi,

1 day course + public = FREE??

 

[aji_vlsi]

aji_vlsi,

1 day course + public = FREE??

Sorry if that mislaed you to think so, given that I and my team has put enough energy in creating this course, it is not free. In trainings a "public" class means a class open to audience from many companies. It is at Rs. 7500 /-

Ajeetha, CVC
www.noveldv.com

 

[sarath51]

I guess simulator support has to be there for using TCL . AS far as i know ModelSim has that capability .
Long time back i reffered to doulos trainig website . Ignore if u all ready aware of these links.Meanwhile i shall try to do some experiments

https://www.doulos.com/knowhow/tcltk/examples/modelsim/
https://www.doulos.com/knowhow/tcltk/examples/
**broken link removed**

 

[aji_vlsi]

Modelsim, VCS and NC all have good TCL support in recent releases.

Ajeetha, CVC
www.noveldv.com