modulo 5 counter
graciousparul,
A.Anand Srinivasan's suggestion is a good one. I would add one caution, however. In going from state 011 to 100, there is a potential race problem. If the 1st (LSB) stage is slower thatn the 3rd (MSB) stage, then there will be a momentary pulse from the and gate, causing the counter to reset after state 011. By placing a small delay (maybe as simple as an RC low pass filter) between the And gate output and the reset inputs, this "trash pulse" can be eliminated.
Regards,
Kral