How to constrain Xilinx ISE not to connect module pins to PADs?

[msdarvishi]

Hello everybody,

I am working on a design using Xilinx ISE 14.7 and Isim as the simulator with Virtex-5 (XC5VLX50T) FPGA. While I do the post place and route simulation, the PLACE&ROUTE tool connects the outputs of my top module to PADs in FPGA.
I heard there is a way to constrain the design, not to connect the top module pins to the PADs and simulation the design as an ASIC ! But I do not know how to apply those constraints to the design.

I would cordially appreciate any help regarding this issue.

Thanks,

 

[barry]

Huh? You can't route an FPGA and then call it an ASIC. The routing depends specifically on the hardware it's targeting. What is it you are really trying to do? Why DON'T you want your outputs connected to pads? If you don't care about the contributions of the pads, then just look at the signals beofre the pads for your simulation.

 

[msdarvishi]

Huh? You can't route an FPGA and then call it an ASIC. The routing depends specifically on the hardware it's targeting. What is it you are really trying to do? Why DON'T you want your outputs connected to pads? If you don't care about the contributions of the pads, then just look at the signals beofre the pads for your simulation.

Hi,
Thanks @Barry for you reply. I know that FPGA is different as ASIC, it was only an example. I also know that the signals of my top module will be connected to PADs while doing post place and route simulation.
The reason that I am trying to avoid signals to PAD connection is their long routing delay ( in the range of nsec) that destroys the functionality of my top module that is a TDC with the resolution of some psec. Can you please let me know how can I avoid PAD effects in my post place&route simulation?

Thanks,

 

[barry]

I'm afraid I still don't understand. If you don't want to look at the pad effects, don't look at them! Your simulator can look at signals anywhere you chose.

 

[TrickyDicky]

What is the purpose? If you have a design that wont work when connected to pads, your design is not going to work in hardware. So why bother? If you are trying to make an asic, why don't you use an asic tool rather than fpga?

 

[vGoodtimes]

You can use -iobuf for the synthesis step to avoid iobuf insertion. I don't think you can run bitgen if you do this, but IIRC you can still run MAP/PAR.

This type of method is very useful for getting an upper bound on the performance of some HDL construct. It is very useful for quick sandbox designs, or to see how the tools will synthesize/implement modules in the design. I highly recommend doing this from time to time even for simple constructs. It is useful to know what can and can't be done in one cycle on the device you are actually using.

 

[msdarvishi]

You can use -iobuf for the synthesis step to avoid iobuf insertion. I don't think you can run bitgen if you do this, but IIRC you can still run MAP/PAR.

This type of method is very useful for getting an upper bound on the performance of some HDL construct. It is very useful for quick sandbox designs, or to see how the tools will synthesize/implement modules in the design. I highly recommend doing this from time to time even for simple constructs. It is useful to know what can and can't be done in one cycle on the device you are actually using.

Hello @vGoodtimes ,

Thanks for your reply. It seems that your hint to use -ibuf will be useful but I did not get your point how to use it in my design. Can you provide more explanation and an example, if possible, please?

Thanks and Regards,

 

[vGoodtimes]

In the sythesis settings there is an option for this, and that options sets the -iobuf argument to xst. I think the GUI label is something similar to "insert IO buffers", but I am not sure.

My point was that not inserting IO buffers is very useful in determining the best possible performance of the circuit. This can be used to see if some idea is feasible. For your case, if your TDC could meet the desired tolerance before considering IO.

However, I encourage testing out small designs without IOB's. Part of design is knowing what can be done in one cycle. For example, can a 32b addition be done in one cycle for your design? what about a 32b (a + b < c) operation? what about 64 bit operations?