How to constrain the PLL controller ?

[horzonbluz]

I am doing a DFT flow on chip level. I don't know how to constrain the PLL controller.
Below is my constrain about PLL controller
set_dft_signal -hookup_pin {CLOCKGEN/SYS_MUX/Y} \
-pllclocks { CLOCKGEN/i_pll_analog/CLK_OUT } \
-ateclock XREF \
-test_mode_port XTEMD \
-ctrl_bits [ 0 CLOCKGEN/TEST_MODE 1 ]
But it has a warning: unknown command '0'.
Who can tell me how to constrain the PLL controller?

 

[santhosh007]

dft hookup_pin

I am doing a DFT flow on chip level. I don't know how to constrain the PLL controller.
Below is my constrain about PLL controller
set_dft_signal -hookup_pin {CLOCKGEN/SYS_MUX/Y} \
-pllclocks { CLOCKGEN/i_pll_analog/CLK_OUT } \
-ateclock XREF \
-test_mode_port XTEMD \
-ctrl_bits [ 0 CLOCKGEN/TEST_MODE 1 ]
But it has a warning: unknown command '0'.
Who can tell me how to constrain the PLL controller?

I think the way you provide the -ctrl_bits is wrong. you need to constraint the CLOCKGEN to 0 spearately and same as TEST_MODE

 

[sunilbudumuru]

use of test enable signal in dft

Hi Friend,

ATEclk and refclk both need to be defined as -type ScanClock and -type Oscillator.

set_dft_signal -view existing \
-type ScanClock -port ATEclk \
-timing [list 45 55]

dc_shell> set_dft_signal -view existing \
-type Oscillator -port ATEclk

and then, u give the following additionla switches.

set_dft_signal -hookup_pin {CLOCKGEN/SYS_MUX/Y} \
-pllclocks { CLOCKGEN/i_pll_analog/CLK_OUT } \
-ateclock XREF \
-test_mode_port XTEMD \
-ctrl_bits [ 0 CLOCKGEN/TEST_MODE 1 ] \
-type Oscillator \
-view existing

this might work. Pls. let us know if it worked or not.

Regards,
Sunil Budumuru

 

[horzonbluz]

dft basic questions

Can you explain it more clearly?
I use the TEST_MODE signal as the control signal of my pll controller.
When TEST_MODE =0 , the output of my pll controller is CLK_OUT.
When TEST_MODE =1, the output of my pll controller is TST_CLK.

 

[sunilbudumuru]

dft test_mode

Okay,

If I'm correct, u r not working on at-speed testing. And u just want to bypass the PLL controller for normal DFT insertion. If it is the situation things will be more easy.

Assumptions, TST_CLK is a toplevel port.

While developing the DFT script itself, add A MUX at the output of the controller and during SCAN test, TESTMODE will be 1 and you can have the TST_CLK as yout SCANtest clock. And during FUNCTIONAL mode TESTMODE will be 0 and you will have the FUNCTIONAL clock, CLK_OUT.

After reading your design into DFTC, add this script. (Please verify ur MUX functionality from ur LIB and if necessary modify the script accordingly)
################################
current_design TOP
### Take a Multiplexer from LIB
create_cell mux_for_bypass_pll [get_lib_cells slow/MX2X1 ]

### Get down the cell to which the PLL clock output(CLK_OUT) is connected.
get_cell XYZ

# disconnect the PLL Clock output net
disconnect_net CLK_OUT [get_pins XYZ/CK ]

# make the proper connections
connect_net CLK_OUT [ get_pins mux_for_bypass_pll/A ]
create_net A
connect_net A [ get_pins mux_for_bypass_pll/Y ]
connect_net A [ get_pins XYZ/CK ]
connect_net TST_CLK [ get_pins mux_for_bypass_pll/B ]
connect_net TEST_MODE [get_nets ] [ get_pins mux_for_bypass_pll/SEL ]
link
############################################

once it is done, add this at proper location of ur script.

set_dft_signal -view existing_dft \
-hookup_pin [get_pins mux_for_bypass_pll/Y] \
-type ScanClock \
-port TST_CLK \
-timing [list 45 55 ]



Hope this solves your problem.

Regards,
Sunil Budumuru.

 

[horzonbluz]

tst_clk

HI, sunilbudumuru. I have modified my script file according to your advice.
But the warning is still as same as before.

 

[sunilbudumuru]

set_dft_signal hookup_pin

Pls confirm if u r working onSCAN inseriton for @-speed testing.

-SunilB

Added after 12 minutes:

Hi Friend,

To explain the situation more clear, from the pic (attached), u have a clock divider (in your case PLL ). If your design looks the same way, u just do as mentioned in the solution part of attachment. The 2nd pin of mux should connect to your TST_CLK).

If any other specifications at the clock controlling part, pls let us know.

 

[horzonbluz]

dft questions

Yes, my design as your pic described. I just use this kind method to control my out clock of PLL and my test clock.

 

[sunilbudumuru]

About DFT questions

Hi Friend,

Thats nice to hear tht it helped.

Regards,
Sunil Budumuru.