dft test_mode
Okay,
If I'm correct, u r not working on at-speed testing. And u just want to bypass the PLL controller for normal DFT insertion. If it is the situation things will be more easy.
Assumptions, TST_CLK is a toplevel port.
While developing the DFT script itself, add A MUX at the output of the controller and during SCAN test, TESTMODE will be 1 and you can have the TST_CLK as yout SCANtest clock. And during FUNCTIONAL mode TESTMODE will be 0 and you will have the FUNCTIONAL clock, CLK_OUT.
After reading your design into DFTC, add this script. (Please verify ur MUX functionality from ur LIB and if necessary modify the script accordingly)
################################
current_design TOP
### Take a Multiplexer from LIB
create_cell mux_for_bypass_pll [get_lib_cells slow/MX2X1 ]
### Get down the cell to which the PLL clock output(CLK_OUT) is connected.
get_cell XYZ
# disconnect the PLL Clock output net
disconnect_net CLK_OUT [get_pins XYZ/CK ]
# make the proper connections
connect_net CLK_OUT [ get_pins mux_for_bypass_pll/A ]
create_net A
connect_net A [ get_pins mux_for_bypass_pll/Y ]
connect_net A [ get_pins XYZ/CK ]
connect_net TST_CLK [ get_pins mux_for_bypass_pll/B ]
connect_net TEST_MODE [get_nets ] [ get_pins mux_for_bypass_pll/SEL ]
link
############################################
once it is done, add this at proper location of ur script.
set_dft_signal -view existing_dft \
-hookup_pin [get_pins mux_for_bypass_pll/Y] \
-type ScanClock \
-port TST_CLK \
-timing [list 45 55 ]
Hope this solves your problem.
Regards,
Sunil Budumuru.