I think there are 2 issues:
1) what is your Layout extractor? If you're usiing Cadence design flow, the parasitic extraction does not model the lines parasitic inductance, but only some RC (also distributed) model. This can be the reason of the freq. shift, but measurements can be worst!
2) you need have an RLC model of your interconnection path; an electromagnetic simulator can help (like ADS Momentum).
In my experience both C & L parasitic can afect a lot the performances at 5 GHz!
I hope it can help
Mazz