tsillen
Junior Member level 1
Hello,
I have made my clk div code, adc code and DAC code and generated the FIR filter using XILINX's FIR COMPILER 6.3 for my spartan 6 FPGA.
My filter is running on 25MHz , adc and dac on 48kHz.
Now I have the following questions regarding connecting it to the AXI-4 FIR IP block;
1. Since my filter is running on 25MHz and the rest on 48kHz , I assume I need a FIFO (between ADC and FIR , FIR and DAC) in order to convert between the different clocks correct?
2. Since the ADC gets a whole sample in 1 rising edge adc clk (48 kHz) wouldn't the tready and tvalid AXI4 signals for that always be high (or should I put them low on the falling edge?)
I have done a good amount of research online but can't find much information regarding this.
I'd guess these are simple questions but hard to find answers for.
Any help and or tips are appreciated.
Any help or tips are appreciated .
I have made my clk div code, adc code and DAC code and generated the FIR filter using XILINX's FIR COMPILER 6.3 for my spartan 6 FPGA.
My filter is running on 25MHz , adc and dac on 48kHz.
Now I have the following questions regarding connecting it to the AXI-4 FIR IP block;
1. Since my filter is running on 25MHz and the rest on 48kHz , I assume I need a FIFO (between ADC and FIR , FIR and DAC) in order to convert between the different clocks correct?
2. Since the ADC gets a whole sample in 1 rising edge adc clk (48 kHz) wouldn't the tready and tvalid AXI4 signals for that always be high (or should I put them low on the falling edge?)
I have done a good amount of research online but can't find much information regarding this.
I'd guess these are simple questions but hard to find answers for.
Any help and or tips are appreciated.
Any help or tips are appreciated .