AXI-4 doesn't have signals named tready and tvalid it has signals named awready, awvalid, wready, wvalid, bready, bvalid, arready, arvalid, rready, rvalid.
Seems to me what you haven't done an online research for is the AXI-4 spec.
AXI-4 doesn't have signals named tready and tvalid it has signals named awready, awvalid, wready, wvalid, bready, bvalid, arready, arvalid, rready, rvalid.2. Since the ADC gets a whole sample in 1 rising edge adc clk (48 kHz) wouldn't the tready and tvalid AXI4 signals for that always be high (or should I put them low on the falling edge?)
I have done a good amount of research online but can't find much information regarding this.
I'd guess these are simple questions but hard to find answers for.
The source generates the VALID signal to indicate when the
address, data or control information is available. The destination generates the READY signal to indicate that it can
accept the information. Transfer occurs only when both the VALID and READY signals are HIGH.
On master and slave interfaces there must be no combinatorial paths between input and output signals.
A source is not permitted to wait until READY is asserted before asserting VALID.
Once VALID is asserted it must remain asserted until the handshake occurs, at a rising clock edge at which VALID
and READY are both asserted.
A destination is permitted to wait for VALID to be asserted before asserting the corresponding READY.
If READY is asserted, it is permitted to deassert READY before VALID is asserted.
If possible.. I strongly recommend to run both circuits with the same clock.My filter is running on 25MHz , adc and dac on 48kHz.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 process (clk_inadc) begin if rising_edge(clk_inadc) then if (tready = '1' and tvalid = '1') then -- do this because data has been transferred. else -- do this until data is transferred, usually nothing end if; end if; end process;
Yes, if there's actually a 48k clock. Reviewing post #1, the bad idea at the start is to drive the ADC module by a divided clock.But won't this FIFO with independent clocks do the same as the solution mentioned above ?
Yes, if there's actually a 48k clock. Reviewing post #1, the bad idea at the start is to drive the ADC module by a divided clock.
Instead of using a FIFO, you can still synchronize the 48 k into the 25M domain and convert it into a clock enable.
I neither suggested an independent 48 kHz clock, it's just useless.Why would it only work when it is an actual 48kHz clock and not one that is derived from the main clock?
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_unsigned.ALL; entity ADC is port( clk_inadc : in STD_LOGIC; clk_adc : out STD_LOGIC; adc_OF : in STD_LOGIC; adc_in : in STD_LOGIC_VECTOR(11 downto 0); adc_out : out STD_LOGIC_VECTOR(15 downto 0) := (others => '0'); adc_tvalid : out STD_LOGIC := '0'; adc_tready : in STD_LOGIC; clk50 : in STD_LOGIC ); end ADC; architecture ADC of ADC is --signal adc_in_buff : STD_LOGIC_VECTOR(11 downto 0) := (others => '0'); signal clk48kHz_f : STD_LOGIC := '0'; signal clk48kHz_ff : STD_LOGIC := '0'; signal adc_valid : STD_LOGIC := '0'; begin process(clk50) begin if rising_edge(clk50) then if adc_valid = '1' then adc_out(11 downto 0) <= adc_in; end if; end if; end process; process(clk50) begin if rising_edge(clk50) then clk48kHz_f <= clk_inadc; clk48kHz_ff <= clk48kHz_f; adc_valid <= clk48kHz_f and (not clk48kHz_ff); end if; end process; clk_adc <= not clk_inadc; adc_tvalid <= adc_valid when adc_tready ='1' else '0'; end ADC;
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