how to connect matrix keypad to a Cyclone FPGA

[matrixofdynamism]

I have a small matrix keypad encoder design that I wish to test on my FPGA board. I shall make a matrix keypad on a seperate PCB and connect it to the GPIO socket of the DE-115 board. It has a Cyclone IV on it.

In the design, all the inputs to the encoder are pulled high by default. These inputs come from "columns" of the keypad. The FPGA pulls one "row" low at a time and cycles through every all 4 rows on the 4x4 keypad in sequence. The row, not driving low is driven high. When a key is pressed, the row and column are shorted together this if the key is on a row which is pulled low by the FPGA, the column input corresponding to it on the FPGA shall go low too.

Is it safe to use external pull up to 5V with Cyclone IV? What options do I seleect in the GUI to make the design aware of this?

The FPGA may also be driving a pin which is pulled high. What resistance value should I use? Is this safe?

 

[FvM]

Recent FPGAs are not 5V tolerant and shouldn't be connected to 5V pull-ups. Software selectable PCI clamp diodes can partly protect the inputs, but the diodes are inactive before the FPGA configuration (user mode) starts.

You can use internal weak pull-ups instead. You also shouldn't drive the inactive rows high, because you get shorts when multiple keys are pressed simultaneously. Instead operate the row ouputs as open drain driver.

 

[matrixofdynamism]

What if I use a lower voltage, I was going to get the DE-115 board to get the pull voltage as well.
If I do not use external pull up or pull down and wait for the row to be connected to column so one FPGA output can drive another input pin, how would the column input pin behave since it will be floating unless a key is pressed?

 

[FvM]

The suggestion was to use FPGA internal pull-ups which can be enabled in Quartus software per pin.

 

[matrixofdynamism]

aha, so the inputs (columns) use internal weak pull-ups and the outputs (rows) use open drain output. Now it is clear.

If the outputs are not open drain, does an option exist to make them so?

The reason for posting this question is that I really do not want to damage my DE-115 board.

 

[ads-ee]

You emulate an open drain output by coding a tristate that is driven by the output signal:

// For an active high internal signal out_sig driving an emulated active low open drain pin.
assign pin_open_drain_b = out_sig ? 1'b0 : 1'bz;  // out_sig high drives a low on pin_open_drain_b

Regards