How to Connect External Memory to Altera FPGA

[talkyztalky]

hello
im trying to implement a ddr2 controller using altmemphy and i have some questions, can someone help me please?

 

[mrflibble]

Re: ddr2 controller using altmemphy

hello
im trying to implement a ddr2 controller using altmemphy and i have some questions, can someone help me please?

1) instead of expecting us to spend time asking you all sorts of questions in an effort to help you, how about ... YOU take the time to make a proper post describing what you are trying to do, what you have done so far, and problems you encounter. I am not going to waste time guessing to compensate for complacency.

2) please don't PM people (myself included) with random questions. There's a forum for that. Thank you.

 

[talkyztalky]

Re: how to connect External memory to altera fpga

ok sorry for that it's my first time
here's what im trying to do:

i generated in quartus a DDR2 SDRAM Controller with ALTMEMPHY v13.1
and there's an example generated with the megafunction
i set the example as top level entity and compilation is done,
then i am trying to simulate it using modelsim

the problem is : when i generate it as vhfl , the simulation of the testbench is successful
but when i generate it as verilog , the simulation of the testbench doesn't start (clock and reset changes, but there's no pll reset and lock)

thank you

 

[talkyztalky]

Re: how to connect External memory to altera fpga



please if someone can help me

 

[talkyztalky]

Re: how to connect External memory to altera fpga

i am sorry for disturbing you but i really need help, i need to see the simulation to understand the functionality of the driver given by altera so i can write my own.

here is the simulation of the testbench generated with the altmemphy, including the driver,the instance of the controller and the memory model. the testbench does multiple writes and reads on the memory model.

when i run the simulation here is what i got (while generating the controller in verilog and the project in verilog), it seems that the simulation started but the signals doesn't change.

while when generating the same example under vhdl i got the simulation working and the test included in the testbench is fully working.

i can't figure out why the simulation works in vhdl and doesn't work in verilog.

(i included needed librairies and compiled the generated files and the testbench)

here is an image showing the same example but in vhdl

 

[FvM]

Re: how to connect External memory to altera fpga

I'm liberately willing to assume that you don't barely bump the thread but wanted to give additional information. However, what is it? What do we see in the simulation waveform?

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You are talking now about "everydays" simulator operation problems, nothing specific to external memory interface.

You may have run in the problem that standard Modelsim editions (also Altera edition) don't support mixed VHDL and Verilog designs for simulation. Or you simply forgot to include some Verilog libraries in simulation. In any case you'll get a warning about "entity not bound" (that's at least the warning in a VHDL project) or similar.

 

[talkyztalky]

Re: how to connect External memory to altera fpga

the weird thing is that i included all the librairies needed, and i am not using mixed vhdl, one language at a time.

 

[FvM]

Re: how to connect External memory to altera fpga

Good. Next step is to "dive" down the design hierarchy to figure out where the clock, control or data flow is cut.

 

[talkyztalky]

Re: how to connect External memory to altera fpga

even if i did nothing than following the user guide?
i didn't modify anything, i generated the controller , set the example_top as top level entity to my project and tried to simulate the given testbench !

 

[talkyztalky]

Re: how to connect External memory to altera fpga

i'm sorry again but i didn't find another thread similar to the difficulity i'm facing, and you are right there's a verilog wrapper,
my last question please, does that mean that i can't simulate it? or even use it on hardware?
thank you very much for your time and sorry again

 

[ads-ee]

Re: how to connect External memory to altera fpga

the weird thing is that i included all the librairies needed, and i am not using mixed vhdl, one language at a time.

You really should not hijack other peoples threads, with your problem regardless if it's similar, especially a thread like this one, where the OP was not responsive enough to suggestions. I'm certain only a small number of forum members are even looking at this thread many have probably put it in their ignore list.

Check the output results of the generated RTL for VHDL and for Verilog. My bet would be the actual core is produced in only one language regardless of the language selection (most likely VHDL as most of Altera and Xilinx's IP is produced outside the US, where VHDL has a much larger presense.), therefore the IP is VHDL with a Verilog wrapper.

If the code produced is entirely in Verilog then start tracing the clock signal through the hierarchy as FvM suggests (this is debugging 101).

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I just had a thought...

What timescale are you using with the Verilog simulation?

I've seen non-operating clocks when people insist on using 1ns/100ps time scales and such...usually FPGA PLL models require 1ps/1ps or 1ns/1ps.

Try 1ps/1ps or 1ns/1ps timescale and your simulation will probably start working for one or the other depending on the default time step they used in the models.

 

[talkyztalky]

Re: how to connect External memory to altera fpga

in the testbench and other sources it's 1ps/1ps

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i'm sorry again but i didn't find another thread similar to the difficulity i'm facing, and you are right there's a verilog wrapper,
my last question please, does that mean that i can't simulate it? or even use it on hardware?
thank you very much for your time and sorry again

 

[FvM]

Re: how to connect External memory to altera fpga

Synthesis of mixed language designs is no problem. You can also perform a gate level (post synthesis) simulation.

 

[ads-ee]

Re: how to connect External memory to altera fpga

in the testbench and other sources it's 1ps/1ps

That means you'll have to debug the example design to find why the clocks don't start up. As a lot of the signals in the Verilog version are Z that might indicate the design hasn't even exited reset and or initialization.

i'm sorry again but i didn't find another thread similar to the difficulity i'm facing, and you are right there's a verilog wrapper,
my last question please, does that mean that i can't simulate it? or even use it on hardware?
thank you very much for your time and sorry again

You don't hijack a thread you start a new one.

I'm just going by what another posted suggested that the Modelsim Altera Edition (or a PE version of Modelsim) doesn't support mixed mode simulation (I don't know that for certain as I don't know what you are running). Your version of Modelsim may very well support mixed mode simulation and there is some other issue. Quartus II could care less about VHDL/Verilog. It will synthesize either and implement it to run on the hardware.

 

[bigdogguru]

I've moved talkyztalky's discussion to a new thread of its own.

 

[mrflibble]

In the screenshot of the verilog based simulation, what is that "endit" entry in the hierarchy? Right above dut. You'll note that that entry is absent in the vhdl based testbench...

 

[talkyztalky]

endit is the name of a process present in the testbench, but i can't find out why it's present in the verilog simulation.

here is the part of the testbench where endit is used

  // this part from testbench.vhd

endit : process
    variable count          : integer := 0;
    variable ln : line;

    begin
        -- Stop simulation after test_complete or TINIT + 600000 clocks
        while ((count < (TINIT_CLOCKS+600000) ) and (test_complete /= '1')) loop
            count := count + 1;
            wait until clk_to_sdram(0)'event and clk_to_sdram(0) = '0';
        end loop;
        if (test_complete = '1') then
            if (pnf = '1') then
                write(ln, now);
                write(ln, string'("          --- SIMULATION PASSED --- "));
                writeline(output, ln);
                ASSERT false REPORT "--- SIMULATION PASSED ---" SEVERITY FAILURE ;
            else
                write(ln, now);
                write(ln, string'("          --- SIMULATION FAILED --- "));
                writeline(output, ln);
                ASSERT false REPORT "--- SIMULATION FAILED ---" SEVERITY FAILURE ;
            end if;
        else
                write(ln, now);
                write(ln, string'("          --- SIMULATION FAILED, DID NOT COMPLETE --- "));
                writeline(output, ln);
                ASSERT false REPORT "--- SIMULATION FAILED, DID NOT COMPLETE ---" SEVERITY FAILURE ;
        end if;
        wait;
    end process;

//////////////////////////////////////

  // // this part from testbench.v
initial
    begin : endit
        integer count;
        reg ln;
        count = 0;

        // Stop simulation after test_complete or TINIT + 600000 clocks
        while ((count < (TINIT_CLOCKS + 600000)) & (test_complete !== 1))
        begin
            count = count + 1;
            @(negedge clk_to_sdram[0]);
        end
        if (test_complete === 1)
        begin
            if (pnf)
            begin
                $write($time);
                $write("          --- SIMULATION PASSED --- ");
                $stop;
            end
            else
            begin
                $write($time);
                $write("          --- SIMULATION FAILED --- ");
                $stop;
            end
        end
        else
        begin
            $write($time);
            $write("          --- SIMULATION FAILED, DID NOT COMPLETE --- ");
            $stop;
        end
    end

 

[mrflibble]

Well there is your difference right there.

In the verilog testbench, disable/comment/remove the "endit" bit, and rerun simulation. With a bit of luck it suddenly works. And if so, then proceed to ask yourself why again you put it (endit) in an initial block.

 

[talkyztalky]

after removing the endit block i got the same result with this log :

# vlog -vlog01compat -work work +incdir+. {top.vo}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module dd_example_top
add wave -position insertpoint sim:/dd_example_top_tb/dut/dd_inst/*
# ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf
# 
#           File in use by: Administrator  Hostname: DELL12  ProcessID: 7428
# 
#           Attempting to use alternate WLF file "./wlfticrrcm".
# ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf
# 
#           Using alternate file: ./wlfticrrcm
# 
# 
# Top level modules:
# 	dd_example_top
# 
add wave -position insertpoint sim:/dd_example_top_tb/dut/driver/*
run 100000
# 
# **********************************************************************
# This testbench includes a generated Altera memory model:
# 'dd_mem_model.v', to simulate accesses to the DDR2 SDRAM memory.
#  
# **********************************************************************
run 100000

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btw i didn't write it, it's automatically generated with the phy from quartus

 

[ads-ee]

Well there is nothing wrong with the vlog compilation. Did you post this snippet of the transcript because of the warnings? The warning is not a problem it only signifies that you probably didn't stop the previous simulation so that it released the wlf file. Exiting Modelsim completely and delete all the wlf files will allow Modelsim to open the default vsim.wlf.

What is the vsim command line look like, it appears that it was left out of your post?

I don't know if you are running the VHDL & Verilog simulations in the same directory, but I would probably try deleting the work library and recreate it, so you start fresh with only the verilog modules complied into the work library. This at a minimum will ensure you aren't using some old module or picking up something compiled for VHDL.

If there are no warnings from vsim after the clean reparse/compile, then it looks like you will have to debug it by tracing the signals back. It's very suspicious that the Verilog simulation is filled with Zs. I would trace the clock back through the hierarchy and try to find out what is stopping it from being generated.