Sthg. you can do is working with black boxes. It is to say, you generate a netlist (i.e. with Synplify) of one part of the code and instantiate it as a component in the vhdl code that is going to be synthetised with the other tool( XST in this case).
If you are using ISE as project manager, you add this netlist as another source file, or if you work in another way, perhaps you will need to add an attribute (see xst help).
Anyhow, using any of the flows/synthesis tools, I recommend you to register inputs to this "black box", and outputs from the "black box". If not there will be logic not optimized and it may give you troubles.