kequal
Newbie level 3
A question of a novice
The logic of one FPGA is divided into two parts which are designed by two men respectively. They use different synthesis tools. One uses xilinx XST and the other uses Synplify. When the two parts of code are combined into one design, neither synthesis tools can assure that these two men could get the same results as they did under their own tools.
We want to generate a package or IP core from one man's design, so when combining the code, the other man needn't synthetize it again.
But we don't konw how to do this, or is there any better ideas to solve the problem?
The logic of one FPGA is divided into two parts which are designed by two men respectively. They use different synthesis tools. One uses xilinx XST and the other uses Synplify. When the two parts of code are combined into one design, neither synthesis tools can assure that these two men could get the same results as they did under their own tools.
We want to generate a package or IP core from one man's design, so when combining the code, the other man needn't synthetize it again.
But we don't konw how to do this, or is there any better ideas to solve the problem?