How to clear these timing errors of DMA controller?

[sudhirkv]

Hello Friends,

I have designed a DMA Controller and i have checked with the funtionality and its working perfect and synthesis report is also clear..

But the point is now i have the 4 timing errors where i have got stucked up. I didnt check this design with the board becoz of some problems here..

Can anyone please tell me how to clear this timing errors... where i have to edit the code so that my code is error free...

As am a newbie i desperately need a help on this regard....

Am using LATTICE ispLEVER 6.1 and Synplify as my synthesis tool..


--------------------------------------------------------------------------------
Lattice TRACE Report, Version ispLever_v61_PROD_Build (37)
Fri Jan 19 03:10:10 2007

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2006 Lattice Semiconductor Corporation, All rights reserved.

Report Information
------------------
Command line: trce.exe -v 1 -o lcd_dma.twr lcd_dma.ncd lcd_dma.prf
Design file: lcd_dma.ncd
Preference file: lcd_dma.prf
Device,speed: LFXP6C,5
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------

BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------



================================================================================
Preference: FREQUENCY PORT "clk" 151.126000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed: The following path meets requirements by 5.284ns
The internal maximum frequency of the following component is 750.751 MHz

Logical Details: Cell type Pin type Component name

Source: FSLICE Clock SLICE_49
Destination: FSLICE Data in SLICE_49

Delay: 1.332ns -- based on Minimum Pulse Width

Report: 750.751MHz is the maximum frequency for this preference.


================================================================================
Preference: FREQUENCY NET "clk_c" 151.126000 MHz ;
4096 items scored, 4 timing errors detected.
--------------------------------------------------------------------------------


Error: The following path exceeds requirements by 0.367ns

Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)

Source: FF Q dmabus_b_state_fast_3 (from clk_c +)
Destination: FF Data in addinc_wd_cnt_5 (to clk_c +)

Delay: 6.854ns (44.7% logic, 55.3% route), 8 logic levels.

Constraint Details:

6.854ns physical path delay SLICE_82 to SLICE_74 exceeds
6.616ns delay constraint less
0.000ns skew and
0.129ns DIN_SET requirement (totaling 6.487ns) by 0.367ns

Physical Path Details:

Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.400 R21C11B.CLK to R21C11B.Q0 SLICE_82 (from clk_c)
ROUTE 3 0.754 R21C11B.Q0 to R21C12B.A1 dmabus_b_state_fastZ0Z_3
CTOF_DEL --- 0.265 R21C12B.A1 to R21C12B.F1 SLICE_148
ROUTE 1 0.638 R21C12B.F1 to R20C12D.C1 dmabus_un5_srcadd_i_a2_0Z0Z_1
CTOF_DEL --- 0.265 R20C12D.C1 to R20C12D.F1 SLICE_134
ROUTE 36 0.478 R20C12D.F1 to R20C12D.C0 dmabus_N_279
CTOF_DEL --- 0.265 R20C12D.C0 to R20C12D.F0 SLICE_134
ROUTE 1 1.095 R20C12D.F0 to R16C12A.M0 addinc_N_7_iZ0
CINTOFCO_D --- 0.583 R16C12A.M0 to R16C12A.FCO SLICE_21
ROUTE 1 0.000 R16C12A.FCO to R16C12B.FCI addinc_un1_wd_cnt_cry_1
FCITOFCO_D --- 0.101 R16C12B.FCI to R16C12B.FCO SLICE_22
ROUTE 1 0.000 R16C12B.FCO to R16C12C.FCI addinc_un1_wd_cnt_cry_3
TLATCH_DEL --- 0.919 R16C12C.FCI to R16C12C.Q1 SLICE_23
ROUTE 1 0.826 R16C12C.Q1 to R17C11A.D0 N_66
CTOF_DEL --- 0.265 R17C11A.D0 to R17C11A.F0 SLICE_74
ROUTE 1 0.000 R17C11A.F0 to R17C11A.DI0 addinc_N_11_iZ0 (to clk_c)
--------
6.854 (44.7% logic, 55.3% route), 8 logic levels.

Clock Skew Details:

Source Clock:
Delay Connection
2.310ns A7.PADDI to R21C11B.CLK

Destination Clock:
Delay Connection
2.310ns A7.PADDI to R17C11A.CLK

Warning: 143.205MHz is the maximum frequency for this preference.

Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "clk" 151.126000 MHz ; | 151.126 MHz| 750.751 MHz| 0
| | |
FREQUENCY NET "clk_c" 151.126000 MHz ; | 151.126 MHz| 143.205 MHz| 8
| | |
----------------------------------------------------------------------------


1 preference not met.

----------------------------------------------------------------------------
Critical Nets | Loads| Errors| % of total
----------------------------------------------------------------------------
addinc_N_11_iZ0 | 1| 4| 100.00%
| | |
dmabus_un5_srcadd_i_a2_0Z0Z_1 | 1| 4| 100.00%
| | |
N_66 | 1| 4| 100.00%
| | |
addinc_un1_wd_cnt_cry_3 | 1| 4| 100.00%
| | |
addinc_un1_wd_cnt_cry_1 | 1| 4| 100.00%
| | |
addinc_N_7_iZ0 | 1| 4| 100.00%
| | |
dmabus_N_279 | 36| 4| 100.00%
| | |
dmabus_b_state_fastZ0Z_8 | 3| 1| 25.00%
| | |
dmabus_b_state_fastZ0Z_5 | 3| 1| 25.00%
| | |
dmabus_b_state_fastZ0Z_3 | 3| 1| 25.00%
| | |
dmabus_b_state_fastZ0Z_6 | 4| 1| 25.00%
| | |
----------------------------------------------------------------------------


Timing summary:
---------------

Timing errors: 4 Score: 1079
Cumulative negative slack: 1079

Constraints cover 6228 paths, 1 nets, and 1070 connections (73.7% coverage)

--------------------------------------------------------------------------------

 

[bansalr]

Re: Timign Errors

constraint the path from and to timing. I thnik it shall be easy.

 

[rsrinivas]

Timign Errors

simple
reduce the frequency by 10% and synthesize again
it should work
good luck

 

[sudhirkv]

Re: Timign Errors

Thanks for u r reply. but the fact is i want to make it run with 200Mhz..... As of now am going to test it with 50 MHz only... If i want to make it run for 200Mhz where i have to change the code... which part of the code decided the clock frequency.. There is three types of addition to my code... if i make it as a funtion will it be helpfull to increse the clock frequency...

 

[rsrinivas]

Timign Errors

make ur code asynchronus it will help increase speed
like
always @(posedge clk or negedge reset)
begin
if(!reset)
--
--
--
else
--
--
--
end
and moreover if ur code works for 50 MHz on an FPGA it is expected to work at 3 times the speed on an ASIC
cheers

 

[sudhirkv]

Re: Timign Errors

I didnt do any corrections in code but i eliminated the timing error by resynthesising the same code and i have checked one option in the tool itself where it will map the netlist till there are no timing errors.. I did that and it was successfull......

time being my problem is over but my doubt still remains that:

1. how the frequcy is determined by the synthesi. which part of the code affects the code...

I guess am clear....