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How to choose the number of Scan-in and Scan-out?

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kiranks9

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Scan chains

For Particular design, how to chose the number of Scan-in and Scan-out?
 

Re: Scan chains

This has to be decided by the tester you plan to use. How many scan channels it can support. MOre the number of scan chains better it is....

If you have multiple tester, you can use multimode where you can have different modes each having different number of scan chains.


-cheers
vlsi_eda_guy
 

Re: Scan chains

U mean to say its depends only on Tester requirements or any other factors. suppose tester supports 500 SCAN-IN and SCAN-OUT, can we put 500 SCAN-IN and SCAN-OUT? let me know
 

Re: Scan chains

well 500 is a hypothetical number ,but yes if the tester can support 500 scan chains then you will get the best results ( tester Applicaton Time ) with 500 scan chians... Also, your chip should have 1000+ pins ;-)
 

Re: Scan chains

no of scan chain depends on multiple factors like
No of IO's available, Total number of flops, target tester capabilities, test time( cost of the device per million parts).
 

Re: Scan chains

Santosh,

can you elaborate how the number of scan chains is controlled by " test time( cost of the device per million parts) and number of flops in the chain". Please talk about a practical design. Dont say that a design with 5 flops cannot have 6 chains.

Also, I would again say it is always best to have the number of scan chains equal to the number that can be supported by the tester.

If you see any scan compression technique,, all we are trying to do is to maximize the number of scan chains.

-cheers
vlsi_eda_guy
 

Re: Scan chains

Absolutely, the number of scan chains is influenced by test time (which determines cost of test, and in turn the COGS ffor your device). The faster you can test a device, the cheaper it is to test, and the cheaper the cost of producing that part is.

Increasing the number of scan chains will reduce the number of flops per chain (i.e., the number of clocks it takes to load/unload a scan vector). This will reduce test time.

Yes, if your device can support it (has enough I/Os to use for scan pins), and the tester can support it, more scan chains is better. But you have to have both. It's not determined by just one or the other.

for DFT talk/info go to:
DFT Digest
DFT Forum
 

Re: Scan chains

vlsi_eda_guy said:
Santosh,

can you elaborate how the number of scan chains is controlled by " test time( cost of the device per million parts) and number of flops in the chain". Please talk about a practical design. Dont say that a design with 5 flops cannot have 6 chains.

Also, I would again say it is always best to have the number of scan chains equal to the number that can be supported by the tester.

If you see any scan compression technique,, all we are trying to do is to maximize the number of scan chains.

-cheers
vlsi_eda_guy

in my previous job, i had a constraint on the test time (maximum time allowed for entire testing ~1.5s bcoz the microcontroller parts sold @ 5-6$ for ppm), in this case i had chosen the maximum number chains (36 chains) to reduce the test time at the same time had a enough IO's thre for sharing. at the same time your tester may have 256 IO's but you may not be able to have the 256 chains becasue there are restictions(like you need to share external IPs..) on the IOs sharing during testmode.
to overcome the IO's availability and the tester resrictions, compression technique is used effectively.
 

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