How to choose sampling rate?

[himadri117]

I am working on a FMCW radar and I want to sample the I/Q signals from the 2 receiving antenna (total 4 channels) simultaneoulsy and send the digital data to computer to extract range and velocity information using FFT. The below diagram is a overall plan.



In the diagram I have shown a ADC with 1MSPS but thats not based on any calculation, just a rough idea as the maximum frequency component is 500kHz. To make it simplier and test for short range I planned to limit the frequency to 100 kHz.

Now my question is how should I senlect the sampling rate? I don't think 2*fmax (Sampling Theorem) is enough for this purpose. The output from the radar frontend are I/Q signals, band limited from 30Hz to 100kHz. My target is to digitize the signal to the best for proper analysis. Should I consider the DAC (used for tuning the frontend) sample number calculated from the minimum and maximum voltage for tuning, to calculate my sampling rate?

 

[Dan Mills]

If the output from the frontend is band limited to 30 - 100K (Or is to 30 - 500K you are unclear?) then I would be sampling at somewhere around 250Ks/s as this easily meets the requirement of the sampling theorem.

Once you neet the requirement of the sampling theorem there is NO MORE information to be obtained by increasing the sampling rate, however your 12 bit converters may limit your dynamic range somewhat.

Regards, Dan.

 

[himadri117]

Thanks for the reply. The output freq is upto 500 kHz but I want to limit the frequency to 100 kHz (using low pass filter). I understand your point using a 250 kSPS for 100 kHz signal, but I have a DAC that needs to tune the radar module under the same clock on which the ADC samples the signal..... the radar module has a bandwidth of 250 MHz (24 Ghz - 24.25 Ghz). As per the radar module datasheet the DAC voltage level for tuning varies from 630mV to 2.3V. Do I need to give preference to the DAC to calculate the sampling rate, so that the sampling number fits in the 250MHz of the radar module.

 

[Dan Mills]

Depends on the frequency of the highest component of your desired modulation waveform (I assume a chirp of some sort).

Meh, you are going into an FPGA anyway, just run everything way fast, you can always decimate in the gate array.

Note, DO NOT, or at least think very carefully before you do, use the on chip fpga PLLs to generate the converter clocks, phase noise is the enemy here and they are never great, best is an external low noise XO.

Regards, Dan (Who used to play similar games in the Sonar industry).