How to choose good VDsat value in CMOS analog design

[hung_wai_ming@hotmail.com]

cmos vdsat

Basically, we have a mindset of VDsat ~200mV in process >0.35um (maybe someone will say "NO", just an example here) and down to DSM, ppl said we can select a smaller VDsat ~100mV, as the headroom for voltage changes from 3.3V to 1.8V, 1.2V, so VDsat can't be too high for device saturation.

For low power design, as bias current is generally very small, so VDsat for a typical NMOS transistor between 0.1uA to 5uA can vary a lot for the same size, ppl will tend to increase the gate length to provide a larger VDsat.

My question here is
(1) How we should choose a proper VDsat value from what criteria?
(2) How we should approach low power design when generally bias current is very small, shall we desparately to increase gate length to fit enough VDsat?
(3) Same as (2) how we should approach low voltage design as headroom becomes less, too high VDsat can make device work properly.

 

[SwordFish]

cmos vdssat

You rise a interesting question.

Till now I didn't see a clear explication for this.

Usualy when I need a maximum voltage range (and a minimum Vds) I choose first the L in such a way to fit the noise/matching and after that I calculate the W to fit the necessary current requirement (like in opamps).
And then with corner simulation I'm extracting the maximum Vdsat from DC output report. This max Vdsat is the min VDS that I should keep in order to have all time my transistor in saturation (that's why I have to make the corner simulation).
If at the end I'm not happy with the result then I make another iteration.
Usualy at the second iteration I'm happy with the result.

I hope that this will help you.

Regard,
SwordFish.

 

[ch1k0]

define vdsat cmos

vdsat less than 125mV is not useful, hard limit of subthreshold vdsat is about 125mV...

 

[hung_wai_ming@hotmail.com]

vdsat cmos

Swordfish

Sometimes, I worked similar as yours.

ck1k0

I seldom work on subthreshold region, except in 32.768K XOSC, so may I understand the reasoning of the "hard limit" and if that's so, how would you tackle the questions I raised in the first message?

Thanks

 

[ch1k0]

vdsat 0.35um

Vgs-Vth less than 0.2 make transistor work in moderate-weak inversion.
Vdsat is ~0.9*(Vgs-Vth) , but never less than Vdsat weak inversion.
Weak inversion vdsat is ~5*Vt , not possible go below ~125mV Vdsat.

No one answer to all (a) (b) (c) question. make L great, use moderate inversion, avoid bad mismatch weak inversion. more stages, more gain.

if low speed, low power, 0.35, 0.25, 0.18 more good for analog.

 

[hung_wai_ming@hotmail.com]

vdsat transistor

ck1k0

How would you develop such descriptions as stated?
From which book ?

 

[didibabawu]

transistor mos vdsat

ck1k0

How would you develop such descriptions as stated?
From which book ?

I also want to know something about it.

 

[ch1k0]

vdsat simulation methodology

ck1k0

How would you develop such descriptions as stated?
From which book ?

any good book ?

Vdsat = (Vg - Vth)/n , n=1.2 , basic equation ?

Push Helped me if useful!!!

 

[WindRay]

measuring vdsat cmos

Hi
It is a very interesting questions.

I guess I will do this method in order to size my transistors:

1. We need to determine the VDSsat value based on the Minimum OPERATING VOLTAGE (VCC). This is to ensure that none of the transistors goes to triode region.

2. With the VDsat that you want to achieve, next we set the length of the transistor. You can follow on SwordFish method. That is using the maximum OPERATING VOLTAGE (VCC). Please note that you want to work in a region in the VI curve as flat as possible. => high and flat (does not change with Vcc range) Ro.

3. Next thing is to size the Width of the transistor based on the ID current to get the VDSsat that you want to achieve in item (1).