This impossible without a second clock or a particular hardware. With Altera FPGA (probably others too), you can use PLL lock signal to detect presence of a clock. When the clock stops, you can disable critical output signal asynchronously from this signal.
P.S.: There is another possibility using logic delay chains. But the technique is strongly disliked by FPGA tools, causing showers of timing errors and such. Also a delay chain ring oscillator could be possibly used for a clock monitor, avoiding external components for this function.