I am writing verilog code for modular inversion algorithm, how write synthesizable verilog code to check a value inside the register is one(1) or not? kindly help on this.
for example if register u=1, then it should return TRUE/some other operation to be continued else FALSE.
how to do for this.
Thank you for the reply. BTW, if u is a 16-bit register or more, can we follow the same method?
Also i need this condition in a while loop but while is not sysnthesizable, how to proceed this.
For example, So until if u!=1,it need to do some operation and when u become 1(u=1), it need to do some other operation.
I suggest you read a verilog tutorial. There are plenty about. Remember, this is NOT software, but hardware. Before you write any code, you should have a circuit diagram of your intended circuit. Verilog is an HDL - hardware description language. How can you write the code if you dont know what circuit you're describing.
I suggest you read a verilog tutorial. There are plenty about. Remember, this is NOT software, but hardware. Before you write any code, you should have a circuit diagram of your intended circuit. Verilog is an HDL - hardware description language. How can you write the code if you dont know what circuit you're describing.
Yes I can understand, I have the algorithm, and i am reading and trying many tutorials to draw circuit diagram from the algorithm, so that only I can write the verilog code correctly. But I cannot get the clear idea of how to draw circuit diagram and write synthesizable verilog code from/for the given algorithm. Actually I am trying to write for extended euclidean algorithm.
the problem is that you are vague in informations.
Give clear informations:
Is it a 16 bit value or not?
If 16 bit value:
Then it´s range is 0..65535
If you want to check for value 1 then you should draw the binary states of all 16 lines.
(hint: 15 lines are LOW, one line is HIGH).
then it should be obvious that you need to compare all the 16 lines for this state.
Several ways to do this.
* a 16 bit input AND logic gate with one input inverted
* or a true 16bit + 16bit input comparator.
Hand draw the circuit on a paper and you are done.
Some considerations regarding synthesis of recursive algorithms.
Iteration loops are a means to describe parallel hardware. Respectively they can be only synthesized if the iteration count is known at compile time. A possible workaround is to implement the iteration for a known maximal iteration count and terminate the loop conditionally.
Alternatively you can rewrite the loop as clocked sequential circuit, performing one iteration step per clock cycle.
I mean that "==" operator in case of registers is comparing them bit by bit (also "===" operator that aditionaly comparing bit by bit "x' and "z" states).