How to characterize effective capacitances of Mosfet and FinFet?

[kah89]

Hi,

How to characterize effective capacitances of Mosfet and FinFet?

I want to create testbenches to be able to characterize the effective capacitance of MOSFET first and then the FinFET,
for example cgs, cgd, cgb, cdb and csb.

Could you please help me with that?

 

[AMS012]

You can print out the cap values through DC operating point simulations. Other way is to configure your FET with an ideal resistance (say 1kohms) and based on the -3-dB frequency from AC sim, you can calculate the cap values. Ideally, both ways should result in similar numbers.

 

[kah89]

Thanks for your answer.
but how to calculate the different capacistances from the 3db freq, for example I need to know the value of cgs, cgd, cgb, csb and cdb.

 

[timof]

Since MOSFET capacitances are voltage-dependent - apply DC voltages to the pins of your device, according to your requirements (or do a DC sweep, if you want to se C-V characteristic), apply AC small-signal (low frequeny - e.g. 1 MHz) to one of the terminals, measure the currents at the other terminals, take its imaginary part, divide omega and by AC voltage amplitude - and you will get a capacitance, like Cgd, Cgs, etc.

Do not forget that SPICE models for FinFETs have parameters (CCOSFLAG, etc.) controlling whether an extrinsic parasitic capacitance (Cgd, Cgs) is turned on or off in SPICE model. There is a "handshake" between SPICE models and parasitic extraction - to avoid parasitic capacitance double counting or zero counting.
E.g., if you do RC extraction, these extrinsic device capacitances are handled by extraction tool, and they are zeroed out in SPICE model.
But wen you do schematic or device-only extracted netlist simulation, extrinsic parasitic capacitances (and resistances - like gate resistance, etc.) are handled by (included in) the SPICE model.

 

[dick_freebird]

In the real world we build ring oscillators burdened
with various FET terminals (times N) per stage, along
with a no-load and a few easily-figured-capacitor
versions (like large area N and P MOS caps) and let
the frequency tell the tale. Enough terminal permutations
and geometry variations and you can get at the individual
params even though each terminal is a sum.

 

[AMS012]

In the real world we build ring oscillators burdened
with various FET terminals (times N) per stage, along
with a no-load and a few easily-figured-capacitor
versions (like large area N and P MOS caps) and let
the frequency tell the tale. Enough terminal permutations
and geometry variations and you can get at the individual
params even though each terminal is a sum.

This sounds interesting. This way, you would only get relative estimates of various cap values, and the absolute numbers. Is that right?