Since MOSFET capacitances are voltage-dependent - apply DC voltages to the pins of your device, according to your requirements (or do a DC sweep, if you want to se C-V characteristic), apply AC small-signal (low frequeny - e.g. 1 MHz) to one of the terminals, measure the currents at the other terminals, take its imaginary part, divide omega and by AC voltage amplitude - and you will get a capacitance, like Cgd, Cgs, etc.
Do not forget that SPICE models for FinFETs have parameters (CCOSFLAG, etc.) controlling whether an extrinsic parasitic capacitance (Cgd, Cgs) is turned on or off in SPICE model. There is a "handshake" between SPICE models and parasitic extraction - to avoid parasitic capacitance double counting or zero counting.
E.g., if you do RC extraction, these extrinsic device capacitances are handled by extraction tool, and they are zeroed out in SPICE model.
But wen you do schematic or device-only extracted netlist simulation, extrinsic parasitic capacitances (and resistances - like gate resistance, etc.) are handled by (included in) the SPICE model.