i think that's a close answer to my problem
well camera is in same position and it doesn't output same image each time but somewhat same
the thing is that i can't take the clk'event and clk='1' for all hsync,vsync and pclk, because these are connected to the i/o ports and they cant operate as clks. if i take them as clk then code synthesises but doesn't implement and gives the following error message:
ERROR
lace:645 - A clock IOB clock component is not placed at an optimal clock
IOB site. The clock IOB component <pclk> is placed at site <IOB_X2Y24>. The
clock IO site can use the fast path between the IO and the Clock buffer/GCLK
if the IOB is placed in the master Clock IOB Site. If this sub optimal
condition is acceptable for this design, you may use the
CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
WARNING and allow your design to continue. However, the use of this override
is highly discouraged as it may lead to very poor timing results. It is
recommended that this error condition be corrected in the design. A list of
all the COMP.PINs used in this clock placement rule is listed below. These
examples can be used directly in the .ucf file to override this clock rule.
< NET "pclk" CLOCK_DEDICATED_ROUTE = FALSE; >
ERROR
ack:1654 - The timing-driven placement phase encountered an error.
However, i took the pclk signal and put it in place where external crystal can be connected to resolve the above error and then pcl'event and pclk='1' works... and i am getting 8.86 Mhz from camera.
The picture captured from the camera and displayed on lcd is shown in figure below (right side) and the picture i tried to capture is also shown below (left side)...
it is difficult to deduce from the above picture where the error may be because i tried to capture the horizontal black line instead of vertical but obtained nearly similar output image