how to caluate Fanout

1. what is Fanout for any design or logic. On what factors the fanout depends and how to calcualte the fanout. For a 2 Input and gate whats the max fanout it can have.

2.how noise margin will ensure the correct logic propagation for driver to reciever.

if Vnm H = VOHmin - VIHmin....
and Vnm L= VILmax - VOHmin...

means if the TTL output stage is the driver and is feed to CMOS input (reciever) then if VOH = 2.4 and VIH =2.0 and VIL= 0.8 and VOL = 0.4 then the nosie margin is around 2.4 - 2.0 = 0.4V so that the signal is propragated with noise margin of 0.4V with out suseptalbe to nosie. if that 0.4V gap decreases to 0 in any case becoze of ground bounce or cross talk then there will be chance of signal getting disturbed. so 0.4 is the safety margin for the signal to be recieved with out prone to Noise. is my understanding true.

Correct me if i am wrong.

Thanks
Kil

Fanout is the number of gates, a gate may be able to drive. Max fanout depends upon what logic family you are working with. in TTL logic fanout is typically around 10. In CMOS the fanout can be a very large number, but the driving gate's propagation delay increases as the number of gate it drives increases.
Kr,
Avi