I have a system verilog file, which contains few parameterized function and few tasks. I need to write VHDL top file, which passes parameters to system verilog functions/task, i dont know how to call the system verilog function/task.
If anybody knows how to call system verilog function/task, please share your knowledge.
In the above link, i can see one VHDL file calling the function which is in another vhdl file, but i want to call system verilog function from vhdl file.
No, you cannot directly call a SV task/function from VHDL, or the reverse.
What you can do is create a set of handshaking signals - one that triggers the start of the task, and another that triggers the end of the task. These signals can be passed through ports at the mixed language boundary, or you can use $signal_spy if your simulator is Modelsim/Questa. The arguments to your tasks/functions will also need to be passed as ports or use $signal_spy.
No, you cannot directly call a SV task/function from VHDL, or the reverse.
What you can do is create a set of handshaking signals - one that triggers the start of the task, and another that triggers the end of the task. These signals can be passed through ports at the mixed language boundary, or you can use $signal_spy if your simulator is Modelsim/Questa. The arguments to your tasks/functions will also need to be passed as ports or use $signal_spy.