how to call system verilog function/task from vhdl file ????

[Kiruthika C]

I have a system verilog file, which contains few parameterized function and few tasks. I need to write VHDL top file, which passes parameters to system verilog functions/task, i dont know how to call the system verilog function/task.

If anybody knows how to call system verilog function/task, please share your knowledge.



Thanks & Regards
Kiruthika C

 

[sivamani]

refer

http://www.altera.com/support/examples/vhdl/v_hier.html
http://www.alteraforum.com/forum/showthread.php?t=24199

 

[Kiruthika C]

refer

http://www.altera.com/support/examples/vhdl/v_hier.html
http://www.alteraforum.com/forum/showthread.php?t=24199

thanks sivamani for your help.

http://www.altera.com/support/examples/vhdl/v_hier.html

In the above link, i can see one VHDL file calling the function which is in another vhdl file, but i want to call system verilog function from vhdl file.

Thanks & Regards
Kiruthika C

 

[sivamani]

pls refer this may help

http://www.xilinx.com/itp/xilinx10/isehelp/ism_p_instantiating_verilog_module_mixedlang.htm

http://www.altera.com/support/kdb/solutions/rd11162011_444.html

http://vhdlguru.blogspot.in/2012/06/how-to-mix-vhdl-and-verilog-files-in.html

also refer

https://www.edaboard.com/threads/119604/

 

[Kiruthika C]

pls refer this may help

http://www.xilinx.com/itp/xilinx10/isehelp/ism_p_instantiating_verilog_module_mixedlang.htm

http://www.altera.com/support/kdb/solutions/rd11162011_444.html

http://vhdlguru.blogspot.in/2012/06/how-to-mix-vhdl-and-verilog-files-in.html

also refer

https://www.edaboard.com/threads/119604/

thanks for your help.My doubt is, is it possible to call a task/function which is inside the System Verilog file from vhdl file ????

 

[dave_59]

No, you cannot directly call a SV task/function from VHDL, or the reverse.

What you can do is create a set of handshaking signals - one that triggers the start of the task, and another that triggers the end of the task. These signals can be passed through ports at the mixed language boundary, or you can use $signal_spy if your simulator is Modelsim/Questa. The arguments to your tasks/functions will also need to be passed as ports or use $signal_spy.

 

[Kiruthika C]

No, you cannot directly call a SV task/function from VHDL, or the reverse.

What you can do is create a set of handshaking signals - one that triggers the start of the task, and another that triggers the end of the task. These signals can be passed through ports at the mixed language boundary, or you can use $signal_spy if your simulator is Modelsim/Questa. The arguments to your tasks/functions will also need to be passed as ports or use $signal_spy.

What you suggested is working and thank you Dave.

Thanks & Regards
Kiruthika C