Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I would simulate the vco by injection of an current impulse in the range of pico-amps (almost noise) and see how long it takes to reach steady state oscillation amplitude.
Hope that helps.
For example, if you using direct phase modulation on VCO, then this settling time will effect the modulation spectrum. Thus this settling time is equivalent to modulation bandwidth this VCO can handle. So How to accurately model this settling time in simulation, how to measure it is of a lot of interesting. Even though normally VCOs in CMOS with loaded Q is small, therefore results a fast settling. But it is not clear to me how to model it. Help please! Thanks.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.