settling time of VCO
For example, if you using direct phase modulation on VCO, then this settling time will effect the modulation spectrum. Thus this settling time is equivalent to modulation bandwidth this VCO can handle. So How to accurately model this settling time in simulation, how to measure it is of a lot of interesting. Even though normally VCOs in CMOS with loaded Q is small, therefore results a fast settling. But it is not clear to me how to model it. Help please! Thanks.