Hi, all: please look at this circuit which can be found in the book writed by Gray.
I find this circuit in the book "CMOS Circuit Design, Layout, and Simulation" writed by R.Jacob Baker too. in this book, Baker said the gain of this circuit is -gm6×(r04||r05), this value can be found in the equation 25-2 in the book writed by Baker.
Is this value is right? and why? and how to confirm the samll signal equivalent circuit?
I'm no expert in analog design but since no one else has replied I thought I might give it a try!
My reasoning goes like this.
M3 is a stiff current source sending a constant current through m4 m5 m6. This establishes a constant voltage drop in m4 and m5 (diode connected). So any small signal input gets absorbed across m6 and m3. So the gate to gate voltage b/w m1 and m2 remains fairly constant. The gain in my opinion should be close to 0.
Correct me if I'm wrong!
sorry i forgot to add roM6 to output gain:
its gain is -gM6 * (roM3||roM6)
ro as rfsystem said is rds
M4 and M5 make voltage shifter.
output of first stage can be drain of M6 or M3.
Exact definition of the separation is important to know only for behaviour modelling. So the input of the first stage is G(M6). The input quantity is voltage. The output of the first stage are two voltages at G(M4) and G(M5). Both are tracking but the difference set the bias of the output stage.
HI, rfsystem:do you mean that the first stage hve two output port? if so, I do not know how to calculate the output resistance of the first stage, because there will be too output resistance of the first stage, so I do not know how to calculate the gain of the first stage.