How to calculate the AGC theoretical gain?

[iVenky]

Here's the circuit that I have used for AGC.

I have attached that image.


It's very clear that the gain of the circuit is

[(rds)/ (rds +R3) ]* [ 1+ Rf/R1].

But the thing is that I don't know how to calculate rds theoretically. Can you help me with this?

Thanks in advance.

 

[LvW]

I cannot see your circuit - the link does not work.

 

[iVenky]

I cannot see your circuit - the link does not work.

Now I have attached the circuit

 

[iVenky]

Come on. Someone please answer this question.

Thanks

 

[LvW]

In a WIEN oscillator an active resistor (JFET, ohmic region) is used as a gain stabilizing element.
To select the proper Rds value I do the following:

* Simulation of the Id=f(Vgs) characteristic for Vds=0.1 volt fixed.
* Display of the ratio Rds=Vds/Id as a function of Vgs and selection of a proper operational point (Rds,nom).

Don't forget: Vds must be small enough to keep Rds in the ohmic region.

 

[iVenky]

In a WIEN oscillator an active resistor (JFET, ohmic region) is used as a gain stabilizing element.
To select the proper Rds value I do the following:

* Simulation of the Id=f(Vgs) characteristic for Vds=0.1 volt fixed.
* Display of the ratio Rds=Vds/Id as a function of Vgs and selection of a proper operational point (Rds,nom).

Don't forget: Vds must be small enough to keep Rds in the ohmic region.

Is that possible to find out Rds theoretically without using simulation?

Thanks in advance.

 

[LvW]

Is that possible to find out Rds theoretically without using simulation?
Thanks in advance.

Of course, if you know in advance the formula for the Id(Vgs) characteristic of the particular FET type.

---------- Post added at 18:00 ---------- Previous post was at 17:34 ----------

As an additional hint: Most probably the FET path (Rds) introduces an inacceptable level of non-linearity/distortion into the amplifier (due to the control mechanism).
In this case, it is advisable to use another resistor in series to Q3 (this, additionally, decreases the peak voltage across the D-S path) and/or place another resistor in parallel to the FET.

 

[FvM]

Assuming a simplified quadratic FET characteristic, the behaviour is completely specicfied by Vth and Idss. You'll notice however, that the parameters have considerable type variation for most available FETs. In so far, you can't predict the exact characteristic, neither in a simulation (that will just put in typical parameters) or other calculation. Your circuit should be tolerant to these parameter variations. This won't be a problem for a reasonably designed AGC circuit, however.

Referring to 2N4861 in particular, it's specified as an analog switch without much "analog" parameters. So you'll have series difficulties to derive variable resistor parameters from the datasheet.

Finally, the shown AGC circuit doesn't work as is. Q2 is always on with possibly dangerous gate current supplied to Q1.

 

[LvW]

Is that possible to find out Rds theoretically without using simulation?
Thanks in advance.

Hi iVenky, another question:

For my opinion, your AGC circuitry looks a bit uncommon (which must be not a disadvantage).
Nevertheless, I like to ask you why you haven't chosen the classical approach of a non-inverting opamp configuration with the grounded feedback resistor replaced by a N-J FET.
In this configuration, the gain is decreased by a rising Rds - and the control circuitry can be realized with a diode (rectification of the negative halfwave) and an R-C parallel configuration (storage of peak values). This is the approach used in positive feedback oscillator circuits (WIEN and similar).