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how to calculate Minimum and maximum path delay through xilinx timing analyzer?

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deepthi.reddy.912

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Hi,

I am doing a project on 4-tap FIR DA Filter. I am using Modelsim and Xilinx ISE 8.2i for that. I want to calculate the minimum and maximum combinational path delay of the specified Filter.

Please tell me how to measure them using xilinx timing analyzer? or by any other tools? And also I need to measure path delays also from each logic block in the design.

Kindly help.
 

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