Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
NAME
set_clock_gate_latency
Specifies clock network latency values to be used for clock-gat-
ing cells, as a function of clock domain, clock-gating stage and
fanout.
Data Types
clock_list list
cg_stage integer
cg_fanout_list string
ARGUMENTS
-clock clock_list
Specifies that the latency must be applied with respect to the
specified clocks. If the -clock option is not specified, the
latency is applied with respect to all clock domains to which
the clock-gating cell belongs.
-overwrite
Specifies that clock latency values previously set on clock-gat-
ing cells should be overwritten.
-stage cg_stage
Specifies the clock-gating stage to which the clock latency data
from the fanout range is applied. Registers are considered as
stage 0.
-fanout_latency cg_fanout_list
Specifies the list of clock-gating cells fanout and clock
latency values; for example, {1-5 0.9, 6-20 0.5, 21-inf 0.3}. A
fanout of 1 to 5 has a latency of 0.9; a fanout of 21 or larger
has a latency of 0.3. If the same latency value is wanted for
the entire fanout range, it can be specified as {1-inf 0.9}.
-transitive_fanout
Specifies that transitive fanout should be used instead of
direct fanout when annotating clock gate latency. Direct fanout
is the default.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.