Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] How to calculate fanout_latency for set_clock_gate_latency ?

Status
Not open for further replies.

promach

Advanced Member level 4
Joined
Feb 22, 2016
Messages
1,199
Helped
2
Reputation
4
Reaction score
5
Trophy points
1,318
Activity points
11,636
Could anyone advise how to calculate the values for -fanout_latency using the following examples ?


Example A

SDAO8CA.png



Example B

m0i73NV.png



Example C

ofBvczC.png
 
Last edited:

Problem solved. See the following :


dc_shell> man set_clock_gate_latency



2. Synopsys Commands Command Reference
set_clock_gate_latency


NAME
set_clock_gate_latency
Specifies clock network latency values to be used for clock-gat-
ing cells, as a function of clock domain, clock-gating stage and
fanout.


SYNTAX
status set_clock_gate_latency
[-clock clock_list]
[-overwrite]
-stage cg_stage
-fanout_latency cg_fanout_list
[-transitive_fanout]


Data Types
clock_list list
cg_stage integer
cg_fanout_list string


ARGUMENTS
-clock clock_list
Specifies that the latency must be applied with respect to the
specified clocks. If the -clock option is not specified, the
latency is applied with respect to all clock domains to which
the clock-gating cell belongs.


-overwrite
Specifies that clock latency values previously set on clock-gat-
ing cells should be overwritten.


-stage cg_stage
Specifies the clock-gating stage to which the clock latency data
from the fanout range is applied. Registers are considered as
stage 0.


-fanout_latency cg_fanout_list
Specifies the list of clock-gating cells fanout and clock
latency values; for example, {1-5 0.9, 6-20 0.5, 21-inf 0.3}. A
fanout of 1 to 5 has a latency of 0.9; a fanout of 21 or larger
has a latency of 0.3. If the same latency value is wanted for
the entire fanout range, it can be specified as {1-inf 0.9}.


-transitive_fanout
Specifies that transitive fanout should be used instead of
direct fanout when annotating clock gate latency. Direct fanout
is the default.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top