Trying to answer :: How to calculate the Capacitance at a node?
For more accuracy you should be having Layout ready.
When you are talking about capacitance two things play role -
1. interconnect parasitic-cap,
2. caps inside device-terminals [ which is captured inside device models, and that is also function of device geometry, voltage, temp etc. ].
For MOS device Source and Drain, parameters like AS, [area of source], AD [area of drain] are used to calculate source/drain area-capacitance, and PS [source-perimeter], PD [drain-perimeter] are used to calculate fringe capacitance; and these capacitors are of reverse junction depletion diode, which forms underneath source & drain, the depletion layer width is voltage dependent and so on.
Do parasitic extraction of the interconnects, with MOS devices having AS, AD, PS, PD & NRD NRS parameters added - during extraction [ some are extracted during LVS some during RC extraction ]. During RC extraction, capacitance can be extracted / netlisted either as lumped or coupled. If power is the only concern - lumped cap extraction should be fine.
Run simulation on the post layout netlist. And yes what erikl said, captab analysis - which is not a separate or independent one - it can be enabled for dc & tran [? i forgot]