Many things matter, which are not usual for an
op amp. Settling time, droop rate, sampling
pedestal. But the amplifier attributes still are
on the table. AVOL (gain error), VIO, CMRR,
PSRR, slew rate (part of settling time) etc. all
are roll-up error contributors which will be
embedded in the eventual digitized data.
JFET input op amp may be the best piece-part
along with an analog switch of low charge
injection. The S/H IC design I've done, used
process PJFET for the analog switch and the
buffer (op amp) front end. You might do it in
CMOS and gain the option of adding auto-zero
(avoiding the need for post-fab trimming and
a process whose stability makes this a long
term solution; a process which is so unreliable
that you are called to run "aging analyses" is
not suited to wafer level or package level
trimming).
Approach to some extent follows technology,
or a technology suited to the approach needs
to be found. Which end is driving you? That
is probably the first order of business, the
constraints and care-abouts.