Constructing a VCO in Verilog A would mean that you are making a linear model of the VCO. This can be implemented using a simple transfer function like wout =Kv/s*Vcontrol. So, you also need to model amplitude limiting, which is very important for phase noise to dominate. Also, you need to model the power supply sensitivity which also puts a ripple of the power supply into the output waveform.
There are a lot of non-idealities you have to model as well. Starting point would need you to get the required gain, Kv. You also can model the non-linearity in the gain as well.