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How to build a VCO behavioral model?

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marylin

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vco design

I was asked to build a vco behavioral model(0.13um CMOS),how do it?

should I design a VCO from the transistor-level or system-level(bottom-up or up-bottom)? how to do it? And what the process of build a behavioral model is ?

thanks!
 

rillyxue

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vco design

you can do it using verilog-A.
and you can also do it with ads or matlab.
 

    marylin

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Vamsi Mocherla

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vco design

Constructing a VCO in Verilog A would mean that you are making a linear model of the VCO. This can be implemented using a simple transfer function like wout =Kv/s*Vcontrol. So, you also need to model amplitude limiting, which is very important for phase noise to dominate. Also, you need to model the power supply sensitivity which also puts a ripple of the power supply into the output waveform.

There are a lot of non-idealities you have to model as well. Starting point would need you to get the required gain, Kv. You also can model the non-linearity in the gain as well.
 

    marylin

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marylin

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Re: vco design

Vamsi Mocherla said:
Constructing a VCO in Verilog A would mean that you are making a linear model of the VCO. This can be implemented using a simple transfer function like wout =Kv/s*Vcontrol. So, you also need to model amplitude limiting, which is very important for phase noise to dominate. Also, you need to model the power supply sensitivity which also puts a ripple of the power supply into the output waveform.

There are a lot of non-idealities you have to model as well. Starting point would need you to get the required gain, Kv. You also can model the non-linearity in the gain as well.


but how can I build the vco model,shoul I copy the mathematical from the book or I can do it myself?
 

northeast1

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Re: vco design

marylin said:
I was asked to build a vco behavioral model(0.13um CMOS),how do it?

should I design a VCO from the transistor-level or system-level(bottom-up or up-bottom)? how to do it? And what the process of build a behavioral model is ?

thanks!


If you use spice simulation, you can use Verilog-A, commonlib of eldo has the vco behavior model.
 

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