xtcx
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Hi friends, my design in spartan 3 requires a heavy clock load. The results of par shows clock load of 6000 and even higher with increased logic. I use a single source clk of 40Mhz since all operations need to be synchronous. Hence I use the DCM output <clk_fx> for all loads. My doubt is, if I add another dcm instance and get another <clk_fx>, can I drive my design synchronously?...Will it give the same performance as before?...Or a single BUFG solves my case?...