anilineda
Member level 3
I am looking to design a axi system with the IP's on a VC707 board in vivado. the IPs are
1. Mblaze 2. central DMA 3. block memory generator
here i want to make Mblaze and central DMA as masters and rest of the things are slaves. In detail, central DMA should be a slave to Mblaze in one side and Mblaze should be a slave to central DMA on other side.
but inorder to happen this, mblaze should have a slave interface port. how to bring that ??
Correct me, if I am totally wrong.
1. Mblaze 2. central DMA 3. block memory generator
here i want to make Mblaze and central DMA as masters and rest of the things are slaves. In detail, central DMA should be a slave to Mblaze in one side and Mblaze should be a slave to central DMA on other side.
but inorder to happen this, mblaze should have a slave interface port. how to bring that ??
Correct me, if I am totally wrong.