Hi,
I am assuming here you are getting Latchup Related DRC Errors for your Layout.
These rules are coded to ensure your design should not result in failure because of CMOS Latch up Problem after fabrication.
To overcome these errors in your layout, you need to go for Latchup Prevention techniques.
There are many prevention techniques for Latchup. Go through your design, layout and find out which will best suit to make your layout DRC clean as well as effective.
Go through this link..
**broken link removed**
Thanks
vlsi123